Electrical Characterization and Modeling of Phase Change Memory arrays

Phase Change Memory is one of the most promising emerging Non-Volatile Memory technology thanks to fast writing operations, long endurance and very good radiation hardness. Although a relevant effort is still being put on design optimization and material analysis, the PCM technology has today reached a significant level of maturity so that test chips containing multimegabit arrays of cells are commonly available for electrical characterization purposes. As a result, a significant amount of statistical information can be provided to the reliability/cell design engineer. The analysis of memory arrays allows the identification of additional/unexpected features which, otherwise, would be difficult to be induced from the analysis of single memory cells, being the actual behavior of the array much more complex and statistical in nature. In this talk we present experimental results collected on array of PCM cells whose analysis allowed the identification of new interesting features of the PCM technology. A physical interpretation of the observed phenomena will be suggested and new models will be presented. The dynamical behavior of an array during both writing operations (SET and RESET) will be described first. Afterwards, we will focus on the SET (erasing) operation where most of the interesting features have been observed: the statistical nature of the erasing curve, the observation of a delay time (or time to shunt formation), the presence of a Random Telegraph Signal on the SET endurance curves. All these features seem to be consistent with a filamentation picture of the crystallization process and, accordingly, we developed a new erasing model which has been successfully used for data analysis. A comparison between the suggested model and what has already been proposed in literature will be discussed

Flash Memory Reliability: an improvement against Erratic Erase phenomena using the Constant Charge Erasing Scheme

This work demonstrates that the erratic erase phenomena present in Flash memories may be drastically reduced using different erasing schemes. In particular, the erratic behavior of a standard box erasing scheme (SBES) and that of the constant charge erasing scheme (CCES) have been measured and compared showing that CCES is more robust against erratic erase. Hole trapping/de-trapping properties related to the erratic phenomena reveal that hole trapping induced oxide degradation is expected to be worst for SBE

Fast Identification of Critical Electrical Disturbs in Nonvolatile Memories

We propose a new methodology for a fast top-down identification of disturbs in large arrays of nonvolatile memories. The new strategy aims at providing the set of all the effective and dangerous disturbs present in a technology with no a priori selection of the physical mechanisms to be targeted. No simulations are needed, and neighbor-cell influence on disturb is empirically taken into account. This top-down strategy requires a limited set of experimental measurements and provides, in a fast "one-shot" approach, a complete disturb assessment, including the effects of new failure mechanisms. Experimental results on nonconventional floating gate Flash test chips are shown and discussed in order to demonstrate the features and the validity of the proposed methodology

Erratic Erase in Flash Memories (Part II): Dependence on Operating Conditions

This paper presents experimental results about the erratic erase phenomena occurring in Flash Memories with the aim of providing a deeper insight into the physical nature of the phenomenon and to deepen the comprehension of charge trapping/detrapping dynamics in tunnel oxides during Fowler-Nordheim erase. The results obtained under different operating conditions as Program/Erase cycling, Ultra Violet light exposure, thermal stress and the analysis of the erratic erase behavior varying the erasing conditions and the tunnel oxide thickness, suggested also possible methods that can be used in order to reduce the erratic erase phenomena

Reliability in Wireless Systems

The objective of this chapter is twofold: from one side, techniques and methodologies of the failure science are introduced for each three development phases; on the other side, some practical examples of these methodologies are shown for the case of wireless systems. During phase 1 the reliability of the entire system can be estimated in a general way thanks to failure analysis predictive tools based on failure probability data/models available for each system component (Reliability Predictive Modeling, RPM). The resulting model can be semi-empirical and, as such, it will be based on a huge amount of data. The Military Handbook is a standard example of this type of predictive methodology. Alternatively (or in addiction), it is possible to take into consideration the physical knowledge of the failure mechanisms that are always supposed to be present. The resulting models allow calculating the MTTF in a more accurate way as a function of some basic physical quantities involved in the failure mechanisms. The knowledge of both models is fundamental to address the first project phases and provides accurate estimates of the system reliability. In addition, the failure models allow selecting the methodologies, the criteria and the characteristic parameters for the accelerated tests performed during design and validation phases. Examples of instruments used during phase 1 and related to reliability prediction and modelling will be discussed in section 2 and will consider electronic devices such as MESFET and, semiconductor memories, and some physical mechanisms such as corrosion and ionic migration. The evaluation of the MTTF will also be addressed. Phases 2 and 3 will be discussed in a more general way in sections 3 and 4, where the techniques used in these phases will be applied to a common mobile phone part: the vibrating motor. Issues related to phase 4 will be tackled in section 5 regarding the burn-in, the fault tolerance, the relationship between defects, yield and reliability and the use of redundancy in memories

Flash Memory Reliability: an Improvement Against Erratic Erase Phenomena Using the Constant Charge Erasing Scheme

This work demonstrates that the erratic erase phenomena present in Flash memories may be drastically reduced using different erasing schemes. In particular, the erratic behavior of a standard box erasing scheme (SBES) and that of the constant charge erasing scheme (CCES) have been measured and compared showing that CCES is more robust against erratic erase. Hole trapping/de-trapping properties related to the erratic phenomena reveal that hole trapping induced oxide degradation is expected to be worst for SBE

Reliability of erasing operation in NOR-Flash memories

The erase operation in NOR-Flash memories intrinsically gives rise to a wide threshold voltage distribution causing various reliability issues: read margin reduction; increase of total bitline leakage current and electrical stress during reading and programming. This paper will address and review the erasing operation by analyzing the causes, the reliability issues and the possible solutions of the erased threshold voltage distribution width, the presence of ultrafast bits, the erratic erase phenomenon, the presence of a significant tail (extrinsic behavior) in the erased distribution and the intrinsic oxide degradation during cycling (oxide aging)

Affidabilità di sistemi wireless

La telefonia cellulare rappresenta un sistema di comunicazione personale relativamente recente, originato circa 25 anni fa. Inizialmente i costi di instal-lazione delle infrastrutture di rete, del servizio e dei telefoni cellulari erano tali da limitare la fascia di utilizzo all’utenza commerciale–professionale e la copertura alle grandi città dei paesi a maggior sviluppo industriale. Il rapido e crescente sviluppo tecnologico, accompagnato dall’incremento della clientela, ha permesso ai principali gestori di aumentare la copertura e di diminuire i costi di servizio, effetti che hanno ulteriormente allargato il bacino d’utenza della telefonia cellulare. L’introduzione, nel 1993, delle comunica-zioni digitali e dello standard GSM ha dato il via definitivo al travolgente svi-luppo della telefonia mobile: all’utenza commerciale si è aggiunta l’utenza “consumer”, al servizio principale della telefonia si è aggiunta la possibilità di invio di messaggistica breve (SMS), nata dapprima per esigenze di servizio dei gestori e diventata in seguito una delle principali fonti di introito per i ge-stori di telefonia mobile. La recente introduzione di nuovi standard (GPRS e UMTS) ha aumentato notevolmente le applicazioni legate alla telefonia cellulare: trasmissione dati, trasmissione immagini, trasmissione di musica e video, rendendo la semplice “trasmissione a distanza della voce” una delle tante applicazioni del sistema e non necessariamente la più significativa. I telefoni cellulari, o più correttamente “terminali mobili”, hanno seguito, ma spesso anche pilotato, lo sviluppo delle comunicazioni digitali wireless: dapprima gli obiettivi dei produttori erano la riduzione del peso e delle dimen-sioni, il miglioramento della qualità del segnale vocale, la diminuzione del consumo di potenza per aumentare la durata della batteria. In seguito, il mer-cato dei terminali mobili è stato pilotato da fattori diversi, come la dimensione dello schermo, la possibilità di effettuare foto e video. Queste semplici consi-derazioni, certamente ben note a chi ha seguito, anche come semplice utilizza-tore, l’evoluzione delle comunicazioni digitali wireless, si legano all’argomento del presente capitolo: l’affidabilità dei terminali mobili per tele-fonia cellulare

Reliability of NAND Flash Memories

The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view. The memory reliability represents one of the major antagonist towards this un-stoppable technological evolution, since the correct operations must be assured not only when a new product is presented, but they must be demonstrated for the entire life cycle. In particular, the minimum number of write operations and the ability of keeping unaltered the stored information for years and years must be guaranteed. In this chapter the principal reliability mechanisms affecting the traditional floating-gate NAND flash memories will be addressed: the physical aspects caused by charge transport and trapping in thin insulator layers as well as the in-correct behaviors related to the array architecture. It will also shown as these ef-fects increase dramatically their impact when Multi Level Cells (MLC) are con-sidered. New emerging mechanisms, such as Gate-Induce Drain Leakage (GIDL), Random Telegraph Noise (RTN) and temperature instabilities will also be ad-dressed