듀오-바이너리 송신기와 시간-기반 수신기 회로를 이용한 저전력 고속 디램 인터페이스

DoctorA duo-binary signaling has been applied to a transceiver circuit for a low-power high-speed DRAM interface. The transmitter consists of a half-rate voltage-mode time-interleaved mixing duo-binary driver and a 2-tap feed-forward equalizer. The voltage-mode driver is used in this work because it generates more linear output voltage than the current-mode driver for the duo-binary signaling at low supply voltage. A time-based receiver is used for high-speed operation at low supply voltage. A 1-tap look-ahead decision-feedback equalizer scheme is applied to the time-based receiver for the duo-binary decoding operation. The test chip fabricated in a 28 nm low-power CMOS process gives the energy efficiency of 0.41 pJ/b at 12 Gb/s with a 25 cm-long FR-4 micro-strip line and the supply voltage of 0.75V

A Reduced-Size Look-Up-Table for ADC Sample-Times of a Single-Chip Non-Uniform-Sampling Digital-Beamformer for Ultasound Medical Imaging

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A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS

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A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using A Three-Level Balanced Coding Scheme

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An Analog-Digital-Hybrid Single-Chip RX Beamformer with Non-Uniform Sampling for 2D-CMUT Ultrasound Imaging to Achieve Wide Dynamic Range of Delay and Small Chip Area

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A reduced-size look-up-table for ADC sample-times of a single-chip non-uniform-sampling digital-beamformer for ultrasound medical imaging

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A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using a Three-Level Balanced Coding Scheme

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An Analog-Digital-Hybrid Single-Chip RX Beamformer with Non-Uniform Sampling for 2D-cMUT Ultrasound Imaging to Achieve Wide Dynamic Range of Delay and Small Chip Area

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