A CMOS Multi-phase Delay-Locked Loop for Digital Versatile Disk and Blue-laser Disk

Maste

A 3.8Gbps DRAM DFE-Receiver Circuit with a Single-Loop SS-LMS Algorithm and a 2Gbps LCD Intra-Panel interface circuit with VSYNC-Embedded Clock

DoctorIn this thesis, a 3.8Gbps DRAM interface and a 2Gbps LCD intra-panel interface are proposed.Firstly, a 3.8Gbps 2-drop single-ended integrating DFE (IDFE) receiver is implemented in a 0.18um CMOS by using a single-loop LMS-algorithm to find the DFEcoefficients automatically. Initially, a preamble input data pattern (‘1101’) is applied to the main IDFE circuit to determine the DFE coefficients, while a fixed input data pattern (‘1111’) is applied to the replica IDFE circuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coefficients. The reference voltage (Vref) of preamplifier is generated inside chip by a Vref loop to reduce the effect of the external noise and the input offset voltage of preamplifier and IDFE circuits and also to track the mid-level of the input data swing independent of PVTvariations. An integrating deskew scheme with a minimum overhead is introduced. 2-drop and 4-drop DRAM channels are tested. The maximum data rate was increased from1.0Gbps to 2.6Gbps by DFE in the heavily loaded 4-drop interface, from 3.5Gbps to 3.8Gbps by DFE in the 2-drop interface.Secondly, a clock-cascaded point-to-point intra-panel interface for TFT-LCD is designed to simplify data protocol with high data efficiency. The clock frequency is lowerthan the data rate by sub-pixel bits and the transition time is maximized to reduce harmonics. To simplify the data protocol, the VSYNC is embedded in the clock andcascaded DLLs are used. A simple coarse control scheme is proposed to solve the initial delay problem of DLL and compensate any timing skew between data and clock. Testchip was fabricated in a 0.18um CMOS process. A 2Gbps data transmission was achieved through the FFC length of 100cm and a 50cm FR4 PCB with a 1-tap TX de-emphasis(coefficient 0.4, clock rise time 1.04ns). Image test was performed with 42inch Full HD 120Hz Panel (data rate ~ 1.5Gbps) by using proposed interface and confirmed a correct operation of the proposed protocol

A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

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A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

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A Low-EMI 2Gbps Clock-Aligned-to-Data Intra-Panel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

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The BLADE-ON PETIOLE gene is required for maintenance of the determinats state of organs in Arabidopsis

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