12 research outputs found
κΈλ‘λ² λμ§νΈ μλμ κ΅μ λ΄μ€ - μ¨λΌμΈ κ΅μ λ΄μ€μ λν κ΅κ°λ³ λΉκ΅μ°κ΅¬
μ΄ μ°κ΅¬λ νκ΅μΈλ‘ μ§ν₯μ¬λ¨μμ 2010λ
μ μ§νν κΉμ±ν΄Β·μ¬μμμ κΈλ‘λ² λμ§νΈ μλ κ΅μ 보λ κ²½μλ ₯ κ°νλ°©μμ μλ£ μΌλΆλ₯Ό νμ©νμμμ λ°νλλ€.κΈλ‘λ² λμ§νΈ μλλ₯Ό λ§μ κ΅μ λ΄μ€μ μμ°, μ ν΅ λ° μλΉμ νμ μ μΈ λ³νκ° μΌμ΄λκ³ μλ€. κ·Έλ¬λ μ¨λΌμΈμμ μ 곡λλ κ΅μ λ΄μ€κ° μ€νλΌμΈκ³Ό μ΄λ€ μ°¨λ³μ±κ³Ό 곡ν΅μ μ κ°κ³ μλμ§, κ·Έκ°μ κ΅μ 보λ μ°κ΅¬μμ μ§μμ μΌλ‘ μ κΈ°λ λ¬Έμ κ° μ΄λ μ λ 극볡λκ³ μλμ§μ λν κΈλ‘λ² μ°κ΅¬λ λ§μ§ μλ€. κ²λ€κ° κ΅λ΄ μΈλ‘ μ κ²½μ° λμ§νΈ μλμ λ±μ₯μΌλ‘ μΈν΄ κ΅μ λ΄μ€μ νμ§μ΄ μ
νλκ³ , μλ°© μμ‘΄μ±μ΄ μ¦κ°νλ©°, κ΅μ μ¬νμ λν λ§₯λ½νλ μ 보λ₯Ό μ λ¬νμ§ λͺ»νλ€λ λΉνλ λ§λ€. μ΄ μ°κ΅¬λ μ΄μ νκ΅ λ° μΈκ³ μ£Όμ κ΅κ° κΆμμ§λ€μ μ¨λΌμΈ ν κ΅μ λ΄μ€λ₯Ό μ νν΄ λ΄μ€μ νμκ³Ό λ΄μ©μ λ€μμ±, λ΄μ€μ μ±κ²© λ° λͺ©μ , κΈ°μ¬μ μμ±κ³Ό μλ£ κ΅¬μ± λ° μ 보μ μκ²°μ± λ±μ νκ°νλ€. λμκ° μ°κ΅¬μλ€μ μ΄ μ°κ΅¬λ₯Ό ν΅ν΄ νκ΅ μΈλ‘ μ κ΅μ 보λκ° μκ³ μλ λ¬Έμ μ μ νμΈνλ ννΈ, κ΅μ 보λ νμ§κ°μ μ μν κ·Όκ±°μ ν¨μλ₯Ό λͺ¨μνκ³ μ νλ€. λΆμμ ν΅ν΄ νκ΅ μΈλ‘ κ³Ό μ μ§κ΅ κΆμμ§μ κ΅μ λ΄μ€μλ μλΉν μ°¨μ΄κ° μλ€λ μ μ΄ νμΈλμλ€. νκ΅ μΈλ‘ μ κ΅μ 보λμ κ³ μ§
μ λ¬Έμ μ μ μ¬μ ν λ΅μ΅νκ³ μμκ³ , μΈν°λ·μ λ―ΈνμΈ μ 보μ κ·Όκ±°ν΄ νΈμμ Β·μμμ μΌλ‘ κ΅μ λ΄μ€λ₯Ό νΈμ§Β·κ°κ³΅νκ³ μμμΌλ©°, κ΅μ μ 곡λνμμ λν νκ²½κ°μ κΈ°λ₯μ μ·¨μ½νλ€. μ΄ μ°κ΅¬λ₯Ό κ³κΈ°λ‘ κ΅μ 보λμ λν κ΄μ¬μ κ³ λ λ¬Όλ‘ κ΅μ λ΄μ€μ ν격μ κ³ λ₯Ό μν μ€μ²μ μ λ΅λ€μ΄ μ κ·Ή λͺ¨μλ μ μκΈ°λ₯Ό λ°λλ€
ISP(Innovation Sharing Program)λ₯Ό ν΅ν κ°λ°νλ ₯μ μλ‘μ΄ ν¨λ¬λ€μ λͺ¨μ(Exploring a new paradigm of development cooperation through the Innovation Sharing Program(ISP))
Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs
νμλ
Όλ¬Έ(μμ¬)--μμΈλνκ΅ λνμ :곡과λν μ»΄ν¨ν°κ³΅νλΆ,2020. 2. κΉμ§ν.3D NAND flash memory has become the standard for the modern flash-based storage systems, since contributing an 50% annual growth rate of NAND flash capacity. However, unlike conventional 2D NAND flash memory, 3D NAND flash memory exhibits two contrasting process variability characteristics from its manufacturing process. While process variability between different horizontal layers are well known, little has been systematically investigated about strong process similarity (PS) within the horizontal layer.
In this thesis, based on an extensive characterization study using real 3D flash chips, we show that 3D NAND flash memory possesses very strong process similarity within a 3D flash block: the word lines (WLs) on the same horizontal layer of the 3D flash block exhibit virtually equivalent reliability characteristics. This strong process similarity, which was not previously utilized, opens simple but effective new optimization opportunities for 3D flash memory.
In this thesis, we focus on exploiting the process similarity for improving the I/O latency. By carefully reusing various flash operating parameters monitored from accessing the leading WL, the remaining WLs on the same horizontal layer can be quickly accessed, avoiding unnecessary redundant steps for subsequent program and read operations. Furthermore, we observed that the write sequence of 3D NAND flash memory can be modified so that the effect of our proposed latency optimization techniques can be maximized. Based on this result, we propose a new program sequence, called mixed order scheme (MOS), for 3D NAND flash memory which can further reduce the program latency.
In order to evaluate the effectiveness of the proposed latency reduction techniques with optimized program sequence, we have implemented a PS-aware FTL, called cubeFTL, which manages fast layers and normal layers in a block separately, thus improves the write bandwidth and read latency. We conducted a set of experiments with various benchmarks and I/O traces collected from real word applications. Our evaluation results show that cubeFTL can significantly improve the IOPS by up to 48% over an existing PS-unaware FTL thus enabling high performance 3D flash-based storage systems.3D NAND νλμ λ©λͺ¨λ¦¬λ μ΅μ νλμ κΈ°λ° μ€ν λ¦¬μ§ μμ€ν
μ νμ€μ΄λμλ€. NAND νλμ μ©λμ μ°κ° 50 % μ±μ₯λ₯ μ κΈ°μ¬νκ³ μλ€. κ·Έλ¬λ κΈ°μ‘΄μ 2D NAND νλμ λ©λͺ¨λ¦¬μ λ¬λ¦¬ 3D NAND νλμ λ©λͺ¨λ¦¬λ μ μ‘° νλ‘μΈμ€μ λΉκ΅νμ¬ λ κ°μ§ λμ‘°μ μΈ νλ‘μΈμ€ λ³λ νΉμ±μ λνλΈλ€. μμ΄ν μν μΈ΅λ€ μ¬μ΄μ 곡μ λ³λμ±μ μ μλ €μ Έ μμ§λ§, μν μΈ΅ λ΄μ κ°λ ₯ν 곡μ μ μ¬μ± (PS)μ λν΄μλ 체κ³μ μΌλ‘ μ‘°μ¬ λ λ°κ° κ±°μ μλ€.
μ΄ λ
Όλ¬Έμμλ μ€μ 3D νλμ μΉ©μ μ¬μ©ν κ΄λ²μν νΉμ±ν μ°κ΅¬λ₯Ό λ°νμΌλ‘ 3D NAND νλμ λ©λͺ¨λ¦¬κ° 3D νλμ λΈλ‘ λ΄μμ λ§€μ° μ μ¬ν νλ‘μΈμ€ μ μ¬μ±μ κ°μ§κ³ μμμ 보μ¬μ€λ€. 3D νλμ λΈλ‘μ λμΌν μν λ μ΄μ΄μμλ μλ λΌμΈ (WL) μ¬μ€μ λλ±ν μ λ’°μ± νΉμ±μ λνλΈλ€. μ΄μ μ νμ©λμ§ μμλμ΄ κ°λ ₯ν νλ‘μΈμ€ μ μ¬μ±μ 3D νλμ λ©λͺ¨λ¦¬μ λν λ¨μνμ§λ§ ν¨κ³Όμ μΈ μλ‘μ΄ μ΅μ ν κΈ°νλ₯Ό μ°λ€.
μ΄ λ
Όλ¬Έμμλ I / O λ μ΄ν΄μλ₯Ό κ°μ νκΈ° μν΄ νλ‘μΈμ€ μ μ¬μ±μ νμ©νλ λ° μ€μ μ λλ€. μ ν WLμ μ‘μΈμ€νμ¬ λͺ¨λν°λ§λλ λ€μν νλμ μλ λ§€κ° λ³μλ₯Ό μ μ€νκ² μ¬μ¬μ©ν¨μΌλ‘μ¨ λμΌν μν κ³μΈ΅μμλ λλ¨Έμ§ WLμ λΉ λ₯΄κ² μ‘μΈμ€νμ¬ νμ νλ‘κ·Έλ¨ λ° μ½κΈ° μμ
μ λΆνμν μ€λ³΅ λ¨κ³λ₯Ό νΌν μ μλ€. λν 3D NAND νλμ λ©λͺ¨λ¦¬μ μ°κΈ° μνμ€λ₯Ό μμ νμ¬ μ μ λ μ§μ° μκ° μ΅μ ν κΈ°μ μ ν¨κ³Όλ₯Ό κ·Ήλν ν μ μμμ κ΄μ°°νλ€. μ΄ κ²°κ³Όλ₯Ό λ°νμΌλ‘ νλ‘κ·Έλ¨ μ§μ° μκ°μ λμ± μ€μΌ μμλ 3D NAND νλμ λ©λͺ¨λ¦¬μ λν΄ MOS (mixed order scheme)λΌλ μλ‘μ΄ νλ‘κ·Έλ¨ μνμ€λ₯Ό μ μνμλ€.
μ΅μ ν λ νλ‘κ·Έλ¨ μνμ€λ‘ μ μ λ μ§μ° μκ° κ°μ κΈ°μ μ ν¨κ³Όλ₯Ό νκ°νκΈ° μν΄ cubeFTLμ΄λΌλ PS κ³ λ € FTLμ ꡬννμλ€.μ΄ λΈλ‘μ λΉ λ₯Έ λ μ΄μ΄μ μΌλ° λ μ΄μ΄λ₯Ό κ°λ³μ μΌλ‘ λΈλ‘μΌλ‘ κ΄λ¦¬νμ¬ μ°κΈ° λμνκ³Ό μ½κΈ° μ§μ° μκ°μ ν₯μμν¨λ€. μ€μ λ¨μ΄ μμ© νλ‘κ·Έλ¨μμ μμ§ ν λ€μν λ²€μΉ λ§ν¬ λ° I / O μΆμ μΌλ‘ μΌλ ¨μ μ€νμ μννμλ€. μ°λ¦¬μ νκ° κ²°κ³Όμ λ°λ₯΄λ©΄ cubeFTLμ κΈ°μ‘΄ PS-unware FTLμ λΉν΄ IOPSλ₯Ό μ΅λ 48 % ν₯μμμΌ κ³ μ±λ₯ 3D νλμ κΈ°λ° μ€ν λ¦¬μ§ μμ€ν
μ ꡬνν μ μλ€.Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Contributions 6
1.3 Thesis Structure 9
Chapter 2. Background 10
2.1 3D NAND Manufacturing Process 11
2.2 NAND Flash Program Operation 14
2.3 Read Retries in Read Latency 19
Chapter 3. Process Variability in 3D Flash 21
3.1 Variability Characterization Methodology 21
3.2 Horizontal Intra-Layer Similarity 23
3.3 Vertical Inter-layer Variability 26
Chapter 4. PS-Aware Optimizations 30
4.1 Program Latency Optimizations 30
4.1.1 Elimination of Redundant VFYs 30
4.1.2 Reduction in Number of ISPP Loops 34
4.1.3 Modification in Program Sequence 40
4.1.4 Safety Check for PS-aware Optimizations 48
4.2 Read Latency Optimization 45
Chapter 5. CubeFTL: PS-Aware FTL 47
5.1 Optimal Parameter Setting 49
5.2 Adaptive WL Allocation 51
Chapter 6. Experimental Results 54
6.1 Experimental Settings 56
6.2 Performance Evaluation 56
6.3 Impact of Adaptive WL Allocation 60
Chapter 7. Related Work 63
7.1 Related works 63
Chapter 8. Conclusions 66
8.1 Summary 66
8.2 Future Work 68
Bibliography 69Maste