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    κΈ€λ‘œλ²Œ 디지털 μ‹œλŒ€μ˜ ꡭ제 λ‰΄μŠ€ - 온라인 κ΅­μ œλ‰΄μŠ€μ— λŒ€ν•œ ꡭ가별 비ꡐ연ꡬ

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    이 μ—°κ΅¬λŠ” ν•œκ΅­μ–Έλ‘ μ§„ν₯μž¬λ‹¨μ—μ„œ 2010년에 μ§„ν–‰ν•œ κΉ€μ„±ν•΄Β·μ‹¬μ˜μ„­μ˜ κΈ€λ‘œλ²Œ 디지털 μ‹œλŒ€ κ΅­μ œλ³΄λ„ 경쟁λ ₯ κ°•ν™”λ°©μ•ˆμ˜ 자료 일뢀λ₯Ό ν™œμš©ν•˜μ˜€μŒμ„ λ°νž™λ‹ˆλ‹€.κΈ€λ‘œλ²Œ 디지털 μ‹œλŒ€λ₯Ό λ§žμ•„ κ΅­μ œλ‰΄μŠ€μ˜ 생산, μœ ν†΅ 및 μ†ŒλΉ„μ— ν˜μ‹ μ μΈ λ³€ν™”κ°€ μΌμ–΄λ‚˜κ³  μžˆλ‹€. κ·ΈλŸ¬λ‚˜ μ˜¨λΌμΈμ—μ„œ μ œκ³΅λ˜λŠ” κ΅­μ œλ‰΄μŠ€κ°€ μ˜€ν”„λΌμΈκ³Ό μ–΄λ–€ 차별성과 곡톡점을 κ°–κ³  μžˆλŠ”μ§€, κ·Έκ°„μ˜ κ΅­μ œλ³΄λ„ μ—°κ΅¬μ—μ„œ μ§€μ†μ μœΌλ‘œ 제기된 λ¬Έμ œκ°€ μ–΄λŠ 정도 극볡되고 μžˆλŠ”μ§€μ— λŒ€ν•œ κΈ€λ‘œλ²Œ μ—°κ΅¬λŠ” λ§Žμ§€ μ•Šλ‹€. κ²Œλ‹€κ°€ κ΅­λ‚΄ μ–Έλ‘ μ˜ 경우 디지털 μ‹œλŒ€μ˜ λ“±μž₯으둜 인해 κ΅­μ œλ‰΄μŠ€μ˜ ν’ˆμ§ˆμ΄ μ•…ν™”λ˜κ³ , μ„œλ°© μ˜μ‘΄μ„±μ΄ μ¦κ°€ν•˜λ©°, κ΅­μ œμ‚¬νšŒμ— λŒ€ν•œ λ§₯λ½ν™”λœ 정보λ₯Ό μ „λ‹¬ν•˜μ§€ λͺ»ν•œλ‹€λŠ” λΉ„νŒλ„ λ§Žλ‹€. 이 μ—°κ΅¬λŠ” 이에 ν•œκ΅­ 및 세계 μ£Όμš” κ΅­κ°€ κΆŒμœ„μ§€λ“€μ˜ 온라인 판 κ΅­μ œλ‰΄μŠ€λ₯Ό 선택해 λ‰΄μŠ€μ˜ ν˜•μ‹κ³Ό λ‚΄μš©μ˜ λ‹€μ–‘μ„±, λ‰΄μŠ€μ˜ 성격 및 λͺ©μ , κΈ°μ‚¬μ˜ μž‘μ„±κ³Ό 자료 ꡬ성 및 μ •λ³΄μ˜ μ™„κ²°μ„± 등을 ν‰κ°€ν–ˆλ‹€. λ‚˜μ•„κ°€ μ—°κ΅¬μžλ“€μ€ 이 연ꡬλ₯Ό 톡해 ν•œκ΅­ μ–Έλ‘ μ˜ κ΅­μ œλ³΄λ„κ°€ μ•ˆκ³  μžˆλŠ” λ¬Έμ œμ μ„ ν™•μΈν•˜λŠ” ν•œνŽΈ, κ΅­μ œλ³΄λ„ ν’ˆμ§ˆκ°œμ„ μ„ μœ„ν•œ 근거와 ν•¨μ˜λ₯Ό λͺ¨μƒ‰ν•˜κ³ μž ν–ˆλ‹€. 뢄석을 톡해 ν•œκ΅­ μ–Έλ‘ κ³Ό 선진ꡭ κΆŒμœ„μ§€μ˜ κ΅­μ œλ‰΄μŠ€μ—λŠ” μƒλ‹Ήν•œ 차이가 μžˆλ‹€λŠ” 점이 ν™•μΈλ˜μ—ˆλ‹€. ν•œκ΅­ 언둠은 κ΅­μ œλ³΄λ„μ˜ 고질 적 λ¬Έμ œμ μ„ μ—¬μ „νžˆ λ‹΅μŠ΅ν•˜κ³  μžˆμ—ˆκ³ , μΈν„°λ„·μ˜ 미확인 정보에 κ·Όκ±°ν•΄ 편의적·자의적으둜 κ΅­μ œλ‰΄μŠ€λ₯Ό νŽΈμ§‘Β·κ°€κ³΅ν•˜κ³  μžˆμ—ˆμœΌλ©°, ꡭ제적 κ³΅λ™ν˜„μ•ˆμ— λŒ€ν•œ ν™˜κ²½κ°μ‹œ κΈ°λŠ₯은 μ·¨μ•½ν–ˆλ‹€. 이 연ꡬλ₯Ό κ³„κΈ°λ‘œ κ΅­μ œλ³΄λ„μ— λŒ€ν•œ κ΄€μ‹¬μ œκ³ λŠ” λ¬Όλ‘  κ΅­μ œλ‰΄μŠ€μ˜ ν’ˆκ²©μ œκ³ λ₯Ό μœ„ν•œ μ‹€μ²œμ  μ „λž΅λ“€μ΄ 적극 λͺ¨μƒ‰λ  수 있기λ₯Ό λ°”λž€λ‹€

    Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs

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    ν•™μœ„λ…Όλ¬Έ(석사)--μ„œμšΈλŒ€ν•™κ΅ λŒ€ν•™μ› :κ³΅κ³ΌλŒ€ν•™ 컴퓨터곡학뢀,2020. 2. 김지홍.3D NAND flash memory has become the standard for the modern flash-based storage systems, since contributing an 50% annual growth rate of NAND flash capacity. However, unlike conventional 2D NAND flash memory, 3D NAND flash memory exhibits two contrasting process variability characteristics from its manufacturing process. While process variability between different horizontal layers are well known, little has been systematically investigated about strong process similarity (PS) within the horizontal layer. In this thesis, based on an extensive characterization study using real 3D flash chips, we show that 3D NAND flash memory possesses very strong process similarity within a 3D flash block: the word lines (WLs) on the same horizontal layer of the 3D flash block exhibit virtually equivalent reliability characteristics. This strong process similarity, which was not previously utilized, opens simple but effective new optimization opportunities for 3D flash memory. In this thesis, we focus on exploiting the process similarity for improving the I/O latency. By carefully reusing various flash operating parameters monitored from accessing the leading WL, the remaining WLs on the same horizontal layer can be quickly accessed, avoiding unnecessary redundant steps for subsequent program and read operations. Furthermore, we observed that the write sequence of 3D NAND flash memory can be modified so that the effect of our proposed latency optimization techniques can be maximized. Based on this result, we propose a new program sequence, called mixed order scheme (MOS), for 3D NAND flash memory which can further reduce the program latency. In order to evaluate the effectiveness of the proposed latency reduction techniques with optimized program sequence, we have implemented a PS-aware FTL, called cubeFTL, which manages fast layers and normal layers in a block separately, thus improves the write bandwidth and read latency. We conducted a set of experiments with various benchmarks and I/O traces collected from real word applications. Our evaluation results show that cubeFTL can significantly improve the IOPS by up to 48% over an existing PS-unaware FTL thus enabling high performance 3D flash-based storage systems.3D NAND ν”Œλž˜μ‹œ λ©”λͺ¨λ¦¬λŠ” μ΅œμ‹  ν”Œλž˜μ‹œ 기반 μŠ€ν† λ¦¬μ§€ μ‹œμŠ€ν…œμ˜ ν‘œμ€€μ΄λ˜μ—ˆλ‹€. NAND ν”Œλž˜μ‹œ μš©λŸ‰μ˜ μ—°κ°„ 50 % μ„±μž₯λ₯ μ— κΈ°μ—¬ν•˜κ³  μžˆλ‹€. κ·ΈλŸ¬λ‚˜ 기쑴의 2D NAND ν”Œλž˜μ‹œ λ©”λͺ¨λ¦¬μ™€ 달리 3D NAND ν”Œλž˜μ‹œ λ©”λͺ¨λ¦¬λŠ” 제쑰 ν”„λ‘œμ„ΈμŠ€μ™€ λΉ„κ΅ν•˜μ—¬ 두 가지 λŒ€μ‘°μ  인 ν”„λ‘œμ„ΈμŠ€ 변동 νŠΉμ„±μ„ λ‚˜νƒ€λ‚Έλ‹€. μƒμ΄ν•œ μˆ˜ν‰ μΈ΅λ“€ μ‚¬μ΄μ˜ 곡정 변동성은 잘 μ•Œλ €μ Έ μžˆμ§€λ§Œ, μˆ˜ν‰ μΈ΅ λ‚΄μ˜ κ°•λ ₯ν•œ 곡정 μœ μ‚¬μ„± (PS)에 λŒ€ν•΄μ„œλŠ” μ²΄κ³„μ μœΌλ‘œ 쑰사 된 λ°”κ°€ 거의 μ—†λ‹€. 이 λ…Όλ¬Έμ—μ„œλŠ” μ‹€μ œ 3D ν”Œλž˜μ‹œ 칩을 μ‚¬μš©ν•œ κ΄‘λ²”μœ„ν•œ νŠΉμ„±ν™” 연ꡬλ₯Ό λ°”νƒ•μœΌλ‘œ 3D NAND ν”Œλž˜μ‹œ λ©”λͺ¨λ¦¬κ°€ 3D ν”Œλž˜μ‹œ 블둝 λ‚΄μ—μ„œ 맀우 μœ μ‚¬ν•œ ν”„λ‘œμ„ΈμŠ€ μœ μ‚¬μ„±μ„ 가지고 μžˆμŒμ„ 보여쀀닀. 3D ν”Œλž˜μ‹œ λΈ”λ‘μ˜ λ™μΌν•œ μˆ˜ν‰ λ ˆμ΄μ–΄μ—μžˆλŠ” μ›Œλ“œ 라인 (WL) 사싀상 λ™λ“±ν•œ μ‹ λ’°μ„± νŠΉμ„±μ„ λ‚˜νƒ€λ‚Έλ‹€. 이전에 ν™œμš©λ˜μ§€ μ•Šμ•˜λ˜μ΄ κ°•λ ₯ν•œ ν”„λ‘œμ„ΈμŠ€ μœ μ‚¬μ„±μ€ 3D ν”Œλž˜μ‹œ λ©”λͺ¨λ¦¬μ— λŒ€ν•œ λ‹¨μˆœν•˜μ§€λ§Œ 효과적인 μƒˆλ‘œμš΄ μ΅œμ ν™” 기회λ₯Ό μ—°λ‹€. 이 λ…Όλ¬Έμ—μ„œλŠ” I / O λ ˆμ΄ν„΄μ‹œλ₯Ό κ°œμ„ ν•˜κΈ° μœ„ν•΄ ν”„λ‘œμ„ΈμŠ€ μœ μ‚¬μ„±μ„ ν™œμš©ν•˜λŠ” 데 쀑점을 λ‘”λ‹€. μ„ ν–‰ WL에 μ•‘μ„ΈμŠ€ν•˜μ—¬ λͺ¨λ‹ˆν„°λ§λ˜λŠ” λ‹€μ–‘ν•œ ν”Œλž˜μ‹œ μž‘λ™ 맀개 λ³€μˆ˜λ₯Ό μ‹ μ€‘ν•˜κ²Œ μž¬μ‚¬μš©ν•¨μœΌλ‘œμ¨ λ™μΌν•œ μˆ˜ν‰ κ³„μΈ΅μ—μžˆλŠ” λ‚˜λ¨Έμ§€ WL에 λΉ λ₯΄κ²Œ μ•‘μ„ΈμŠ€ν•˜μ—¬ 후속 ν”„λ‘œκ·Έλž¨ 및 읽기 μž‘μ—…μ— λΆˆν•„μš”ν•œ 쀑볡 단계λ₯Ό ν”Όν•  수 μžˆλ‹€. λ˜ν•œ 3D NAND ν”Œλž˜μ‹œ λ©”λͺ¨λ¦¬μ˜ μ“°κΈ° μ‹œν€€μŠ€λ₯Ό μˆ˜μ •ν•˜μ—¬ μ œμ•ˆ 된 지연 μ‹œκ°„ μ΅œμ ν™” 기술의 효과λ₯Ό κ·ΉλŒ€ν™” ν•  수 μžˆμŒμ„ κ΄€μ°°ν–ˆλ‹€. 이 κ²°κ³Όλ₯Ό λ°”νƒ•μœΌλ‘œ ν”„λ‘œκ·Έλž¨ 지연 μ‹œκ°„μ„ λ”μš± 쀄일 μˆ˜μžˆλŠ” 3D NAND ν”Œλž˜μ‹œ λ©”λͺ¨λ¦¬μ— λŒ€ν•΄ MOS (mixed order scheme)λΌλŠ” μƒˆλ‘œμš΄ ν”„λ‘œκ·Έλž¨ μ‹œν€€μŠ€λ₯Ό μ œμ•ˆν•˜μ˜€λ‹€. μ΅œμ ν™” 된 ν”„λ‘œκ·Έλž¨ μ‹œν€€μŠ€λ‘œ μ œμ•ˆ 된 지연 μ‹œκ°„ κ°μ†Œ 기술의 효과λ₯Ό ν‰κ°€ν•˜κΈ° μœ„ν•΄ cubeFTLμ΄λΌλŠ” PS κ³ λ € FTL을 κ΅¬ν˜„ν•˜μ˜€λ‹€.이 블둝은 λΉ λ₯Έ λ ˆμ΄μ–΄μ™€ 일반 λ ˆμ΄μ–΄λ₯Ό κ°œλ³„μ μœΌλ‘œ λΈ”λ‘μœΌλ‘œ κ΄€λ¦¬ν•˜μ—¬ μ“°κΈ° λŒ€μ—­ν­κ³Ό 읽기 지연 μ‹œκ°„μ„ ν–₯μƒμ‹œν‚¨λ‹€. μ‹€μ œ 단어 μ‘μš© ν”„λ‘œκ·Έλž¨μ—μ„œ μˆ˜μ§‘ ν•œ λ‹€μ–‘ν•œ 벀치 마크 및 I / O μΆ”μ μœΌλ‘œ 일련의 μ‹€ν—˜μ„ μˆ˜ν–‰ν•˜μ˜€λ‹€. 우리의 평가 결과에 λ”°λ₯΄λ©΄ cubeFTL은 κΈ°μ‘΄ PS-unware FTL에 λΉ„ν•΄ IOPSλ₯Ό μ΅œλŒ€ 48 % ν–₯μƒμ‹œμΌœ κ³ μ„±λŠ₯ 3D ν”Œλž˜μ‹œ 기반 μŠ€ν† λ¦¬μ§€ μ‹œμŠ€ν…œμ„ κ΅¬ν˜„ν•  수 μžˆλ‹€.Chapter 1. Introduction 1 1.1 Motivation 1 1.2 Contributions 6 1.3 Thesis Structure 9 Chapter 2. Background 10 2.1 3D NAND Manufacturing Process 11 2.2 NAND Flash Program Operation 14 2.3 Read Retries in Read Latency 19 Chapter 3. Process Variability in 3D Flash 21 3.1 Variability Characterization Methodology 21 3.2 Horizontal Intra-Layer Similarity 23 3.3 Vertical Inter-layer Variability 26 Chapter 4. PS-Aware Optimizations 30 4.1 Program Latency Optimizations 30 4.1.1 Elimination of Redundant VFYs 30 4.1.2 Reduction in Number of ISPP Loops 34 4.1.3 Modification in Program Sequence 40 4.1.4 Safety Check for PS-aware Optimizations 48 4.2 Read Latency Optimization 45 Chapter 5. CubeFTL: PS-Aware FTL 47 5.1 Optimal Parameter Setting 49 5.2 Adaptive WL Allocation 51 Chapter 6. Experimental Results 54 6.1 Experimental Settings 56 6.2 Performance Evaluation 56 6.3 Impact of Adaptive WL Allocation 60 Chapter 7. Related Work 63 7.1 Related works 63 Chapter 8. Conclusions 66 8.1 Summary 66 8.2 Future Work 68 Bibliography 69Maste
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