임피던스 매칭이 된 양방향 다분기 메모리 인터페이스

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 김수환.In this thesis, an impedance-matched bidirectional multi-drop (IMBM) DQ bus is proposed, together with a 4.8Gb/s transceiver for a memory controller which supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. The IMBM DQ bus generates no reflections during write operations, and the reflections that are generated during read operations do not reach the memory controller. Therefore, the IMBM DQ bus transmits and receives both read and write signals without reflective ISI. In addition, the IMBM DQ bus is more tolerant to stub length mismatches than a conventional stub-series terminated logic (SSTL) DQ bus. The proposed DQ bus is applicable to memory system applications which require both high speed operation and high capacity, which the conventional multi-drop and point-to-point bus cannot handle. Because the IMBM DQ bus attenuates the voltage of signals in a manner inversely proportionate to the number of modules, a new clocking architecture is necessary to support the IMBM DQ bus. In this thesis, a 4.8Gb/s transceiver which uses shifted phase-locked loop (PLL) clock is proposed for data sampling instead of the received strobe signal. A prototype memory controller transceiver was designed and fabricated in a 0.13μm CMOS process, and it operates with a 1.2-V supply voltage. Its effectiveness was demonstrated on various measurement configurations. At 4.8Gb/s, this transceiver, with a 4-slot, 8-drop IMBM DQ bus, has an eye opening of 0.39UI in TX mode and 0.58UI in RX mode at a threshold of 10^(-9) BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub-series terminated logic (SSTL) has no timing margin under the same test conditions. Our transceiver consumes 14.25mW/Gb/s per DQ in TX mode and 13.69mW/Gb/s per DQ in RX mode.ABSTRACT I CONTENTS III LIST OF FIGURES V LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 INTRODUCTION TO MEMORY INTERFACE 6 2.1 MEMORY INTERFACE INTRODUCTION 6 2.2 BUS TOPOLOGY 8 2.3 CLOCKING ARCHITECTURE AND CIRCUITS 12 2.4 COMMAND AND ADDRESS ARCHITECTURE 26 2.5 SIGNALING AND TERMINATION SCHEME 32 2.6 EQUALIZATION IN MEMORY INTERFACE 37 2.7 EMERGING TECHNOLOGY 38 CHAPTER 3 IMPEDANCE-MATCHED BIDIRECTIONAL MULTI-DROP DQ BUS 40 3.1 IMPEDANCE-MATCHED BIDIRECTIONAL MULTI-DROP DQ BUS 40 3.2 OPERATION OF IMBM DQ BUS 44 3.3 GENERALIZED IMBM DQ BUS 49 3.4 STEADY-STATE RESISTOR MODEL OF IMBM DQ BUS 55 CHAPTER4 MEMORY CONTROLLER TRANSCEIVER 67 4.1 MEMORY CONTROLLER TRANSCEIVER ARCHITECTURE 67 4.2 TX CIRCUITS OF THE TRANSCEIVER 69 4.3 RX CIRCUITS OF THE TRANSCEIVER 74 4.4 LIMITATION OF THE TRANSCEIVER 79 CHAPTER5 EXPERIMENTAL RESULTS 83 5.1 EXPERIMENTAL SETUP 83 5.2 SINGLE-BIT RESPONSE AND EYE DIAGRAM 87 5.3 BER OF TRANSMITTED SIGNALS (WRITE SIGNALS) 97 5.4 BER OF RECOVERED SIGNALS (READ SIGNALS) 101 CHAPTER6 CONCLUSIONS 109 BIBLIOGRAPHY 111 ABSTRACT IN KOREAN 119Docto