Development of superalloy large exhaust valve spindle by dissimilar inertia welding process

Inertia welding is a solid-state welding process in which butt welds in materials are made in bar and in ring form at the joint face, and energy required for welding is obtained from a rotating flywheel. The stored energy is converted to frictional heat at the interface under axial load. The quality of the welded joint depends on many parameters, including axial force, initial revolution speed and energy, amount of upset, working time, and residual stresses in the joint. Inertia welding was conducted to make the large exhaust valve for low speed marine diesel engine, superalloy Nimonic 80A for valve head of 540mm (21.2") and high alloy SNCrW for valve stem of 115mm (4.53"). Due to different material characteristics, such as, thermal conductivity and flow stress, on the two sides of the weld interface, modeling is crucial in determining the optimal weld geometry and parameters. FE simulation was performed by the commercial code DEFORM-2D. A Good agreement between the predicted and actual welded shape is observed. It is expected that modeling will significantly reduce the number of experimental trials needed to determine the weld parameters, especially for welds of very expensive materials or large shaft. Many kinds of tests, including macro and microstructure observation, chemical composition, tensile, impact, hardness and fatigue test, are conducted to evaluate the quality of welded joints. A variety of tests, including macro and microstructure observation, chemical composition, tensile, impact, hardness and fatigue test, are conducted to evaluate the quality of welded joints. Microstructure and chemical compositions for friction welded joints were carried out using an optical microscope and SEM. The recrystallized and transformed zone were observed from the center line to 3.2 mm of depth in the Nimonic 80A and to 3.5 mm in the SNCrW. The mixed layers of two base materials were observed in the range of 400μm for the welded joint. It has better tensile and yield strength compared to SNCrW and better elongation and reduction of area than that of Nimonic 80A The hardness of the welded joint was measured using the micro Vickers hardness test at room temperature. The fatigue test was carried out with the rotary bending test for base metal and friction welding joints. The fatigue strength for welding joint is 341MPa at 1E+7 cycles. It is higher than that of the SNCrW in 260MPa. Based on the results of the tests, it can be concluded that the inertia welding joints of the superalloy exhaust valve spindle has better properties than the material specification of SNCrW.Abstract = i 기호 설명 = ⅲ List of Tables = ⅴ List of Photographs = ⅵ List of Figures = ⅶ 1. 서론 = 1 1.1 연구 배경 = 1 1.2 연구 동향 = 3 1.3 연구 내용 및 목적 = 5 2. 이론적 배경 = 6 2.1 마찰용접 = 6 2.2 유한요소 기본 방정식 = 10 3. 이종마찰용접 유한요소 공정해석 = 14 3.1 마찰용접 공정해석 = 14 3.2 마찰용접 공정해석 결과 및 고찰 = 18 4. 마찰용접 실험 = 27 4.1 대형 배기밸브 제작 = 27 4.2 마찰용접부 특성 평가 = 32 5. 결론 = 46 참고문헌 = 4

고성능 컴퓨팅 이머징 기술을 위한 회로 및 아키텍쳐 최적화 기법

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 2. 김태환.For system-on-chip (SoC) design improvement in more-than-Moore scale, entirely new high-speed computing technologies beyond conventional optimizations are often proposed. They can solve many limitations of existing designs from different angle of the view. However, as engineers are not mature with such new technologies, these emerging technologies are facing many problems in realization. Even larger implementation overhead than benefits prevents these technologies from being used in real world. This dissertation presents some of the emerging high-speed computing technologies and their limitations in realization, and proposes a solution to each of the technologies to be used in industry with lower technology entry barrier. Firstly, TSV(Through-Silicon Via)-based 3-D IC is introduced for denser chip design by stacking dies vertically. In this dissertation, we solved TSV reliability problem in the clock tree of 3-D IC with a full solution of designing and synthesizing a TSV fault-tolerant 3-D clock tree. Secondly, as clock tree synthesis becomes more complicated under recent design environment of low supply voltage and large variations, asynchronous circuit design have been considered as an alternative to the clock-based synchronous design. In the dissertation, we proposed a new structure of single-rail/dual-rail hybrid asynchronous design that achieves both robustness against variations and low implementation overhead. This design is also devised to be compatible with conventional standard cell libraries and computer-aided design (CAD) tools for productivity and practicality. Lastly, with the aid of clock-less circuit design, biologically inspired neuromorphic computing architecture is emerged to overcome the memory-computation gap in the traditional von Neumann architecture. We improved the performance of the architecture with a new approach of cross optimization of multiple synapse networks in implementation of a deep neural network (DNN).1 INTRODUCTION 1 1.1 TSV based 3-D IC 1 1.2 Asynchronous Circuit Design 2 1.3 Neuromorphic Computing Architecture 3 1.4 Contributions of this Dissertation 4 2 FAULT-TOLERANT CLOCK TREE SYNTHESIS FOR TSV-BASED 3-D IC 6 2.1 Preliminaries 6 2.2 Motivations 11 2.2.1 Limitations of Previous TFU Designs 11 2.2.2 Limitations for Application of Previous TFUs 13 2.3 3-D TSV Fault-Tolerant Clock Tree Synthesis 16 2.3.1 Slew-Controlled TSV Fault-tolerant Unit (SC-TFU) 16 2.3.2 Fault-Tolerant 3-D Clock Tree Synthesis 23 2.4 Experimental Results 33 2.5 Summary 42 3 PRACTICAL ASYNCHRONOUS CIRCUIT DESIGN WITH HYBRID STRUCTURE 45 3.1 Preliminaries 45 3.1.1 Quasi-Delay Insensitive Model 45 3.1.2 Single-rail vs. Dual-rail Asynchronous Circuits 46 3.1.3 Dynamic vs. Static Logic based Asynchronous Circuits 50 3.2 Synthesis of Hybrid Asynchronous Circuits 51 3.2.1 Overview of Hybrid Asynchronous Circuit Structure 51 3.2.2 Design Details for Hybrid Asynchronous Circuits 54 3.2.3 Transformation to the Hybrid Asynchronous Circuit 58 3.2.4 Overall Design Flow 63 3.3 Experimental Results 64 3.3.1 Experiment Setup and Design Models 64 3.3.2 Assessment of Area Overhead 66 3.3.3 Assessment of Power Consumption 68 3.3.4 Assessment of Circuit Performance 72 3.4 Summary 74 4 NEUROMORPHIC COMPUTING ARCHITECTURE OPTIMIZATION SCHEME 76 4.1 Motivation 76 4.2 Preliminaries 77 4.3 Structure Optimization of Neuromorphic Inter-core Architecture 80 4.3.1 Zero Wait Inter-core Architecture 80 4.3.2 Resource Configuration of Inter-core Architecture 84 4.3.3 Using Denaxo-driven Inter-core in Large DNNs 86 4.4 Experimental Results 87 4.4.1 Experiment Setups and Design Models 87 4.4.2 Evaluation of Computation Speed 89 4.4.3 Evaluation of Cell Area 93 4.4.4 Experiments with MNIST Dataset 95 4.5 Summary 96 5 CONCLUSION 97 5.1 Chapter 2 97 5.2 Chapter 3 97 5.3 Chapter 4 98 Abstract (In Korean) 108Docto