Effects of Layout and Process Parameters on Device/Circuit Performance and Variability for 10nm Node FinFET Technology

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Low-Frequency Noise Behavior of La-Doped Hf-Based Dielectric nMOSFETs

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Comprehensive Study of Process-Induced Device Performance Variability and its Optimization for 14 nm Technology Node Bulk FinFETs

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RF performance degradation in 100-nm metal gate/high-k dielectric nMOSFET by hot carrier effects

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Effects of High Pressure Hydrogen Anneal Process on Performance and Reliability in HfO2/SiO2 Dielectric with Contact Etch Stop Layer Stressor

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Conformal, low-damage shallow junction technology (Xj~5nm) with optimized contacts for FinFETs as a Solution Beyond 14nm Node

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