Research and Development of Novel Copper Electroplating Formulas for through Silicon Vias of 3D IC

在過去的 30 年當中，半導體整合技術已經在2 度空間（2D）構裝中廣泛的應用。這樣的技術不但是在電子工業上被廣泛地應用，也在許多相關工業領域上被廣泛地應用，如光電產業、生物機電產業、生醫系統、電子分析、電腦系統、軍事系統、衛星系統、潛艇系統等。從消費性電子到尖端科技產品以及軍事用途上，幾乎所有的工業產品都結合了半導體元件。半導體製程至所以可以如此快速的進展，主要原因之一是MOS 元件具有良好的可尺寸化能力。但是，材料的尺寸是有限的。目前製程能力已經使用銅內連結技術，到達22 奈米。因此，MOS 元件的發展可能將無法再遵守Moore 定律，因為Moore 定律是基於IC 晶片二度空間封裝的考量。為了落實超大型積體電路（VLSI）晶片的高性能，同時還必須限制其電力的消耗，有兩個方式可以進行。一是由電力消耗的觀點，重新考慮線路與系統的架構；另一個方式則是去建構三度空間（3D）的VLSI 結構。在最近的發展的元件當中發現，信號傳遞延遲主要是由線路長度以及引腳電流容量所主導。而3D-VLSI 的結構設計正好可以在不增加電力消耗的條件之下，解決此問題，同時可以大幅提昇元件性能。關鍵性3D-VLSI 的爭議是訊息的傳遞方式與堆疊晶片之間的電力供給，對於此爭議，有許多方法可以來讓晶片互連，例如藉由打線、邊緣連結、電容或電桿結合以及利用穿矽孔（TSV）直接接通等。根據最近的報導，TSV 似乎是很好的候選者，用來解決多功能、高記憶容量以及低耗電量等的需求。這個製程技術需要絕對專業的電化學沈積（ECD）技巧，因此，在此計畫中，吾人提出四個專業的ECD 技術，包含四個特定的電鍍銅配方，這些配方都可以滿足目前TSV金屬化的需求。這四個ECD 銅配方可以快速修補TSV 側壁上的晶種層；可以產生平面式的孔底上移填充TSV 機制；可以做高度選擇性的填銅以及可以直接填充穿矽通孔（TSH）。一旦這些ECD 銅技術開發成功，TSV 製程的步驟、成本都可以大幅地降低。本計畫預計花三年的時間來開發，其中會用到電化學分析技術、臨場電化學掃描穿隧顯微鏡、電極動力學、電鍍銅配方開發技術以及TSV 製程技術，對於3D IC 的TSV 銅金屬化製程而言，是相當完整的一套研發計畫。Semiconductor integration technology has been widely spread in two-dimensional applicationsover the past three decades. This wide application has been employed not only in the field of theelectronics industries but also in a lot of related industries such as optoelectronics, bioelectronics,medical systems, electronics analysis, computer systems, military systems, satellite systems,submarine systems, and so on. From the consumer area to ultra-high-end products and militaryusage, almost all industrial products incorporate semiconductor devices. One significant reason forthis rapid progress is the good scalability of metal-oxide-semiconductor (MOS) devices. However,the scale of materials is limited. Right now, the process capability has arrived at 22 nm using copperinterconnects. Therefore, the development of MOS devices may not follow the Moore law, becausethe Moore law is based on the consideration of 2-dimensional packaging of IC chip.In order to bring out high performance from VLSI chips while restricting their powerconsumption, there are two approaches. One is to reconsider circuits and system architecture fromview point of power consumption. Another is to construct three-dimensional VLSI structure. Inrecent devices, the signal propagation delay is mainly determined by wiring length and pincapacitance. Three-dimensional very large-scale integration (3D-VLSI) is the one solution toimprove performance without increase of power consumption. One of the key issues to realize3D-VLSI is the method of information transfer and the supply of electric power among stackedchips. There are many methods to connect interchip, such as wire-bonding, edge connect, capacitiveor inductive coupling method, and direct contact using through-silicon via (TSV).According to the current reports, TSV seems to be a good candidate to solve the requirement ofmultifunction, high memory capacity, low power consumption and so on. This process technologyneeds absolutely professional electrochemical deposition (ECD) technique. In this work, wepropose four professional ECD techniques, including four specific copper plating formulas, whichcan meet the current demand for TSV metallization. These four copper ECD formulas can result inrapid repair of seed layer coated on the sidewall of TSV, bottom-up filling of TSV in a flat planemode, highly selective copper fill, and in direct filling of through silicon hole (TSH). Once thesecopper ECD techniques are successfully developed, the steps and cost of the TSV process can besignificantly reduced. This plan will take three years to come true, in which electrochemicalanalyses, in situ electrochemical scanning tunneling microscopy (EC-STM), electrode kinetics,formulation of copper plating, and processes development of TSV will be employed in this plan.Therefore, this is a complete plan regarding the TSV copper metallization of 3D IC

穿矽盲孔與通孔之填孔電鍍技術開發

Semiconductor integration technology has been widely spread in two-dimensional applicationsover the past three decades. This wide application has been employed not only in the field of theelectronics industries but also in a lot of related industries such as optoelectronics, bioelectronics,medical systems, electronics analysis, computer systems, military systems, satellite systems,submarine systems, and so on. From the consumer area to ultra-high-end products and militaryusage, almost all industrial products incorporate semiconductor devices. One significant reason forthis rapid progress is the good scalability of metal-oxide-semiconductor (MOS) devices. However,the scale of materials is limited. Right now, the process capability has arrived at 22 nm using copperinterconnects. Therefore, the development of MOS devices may not follow the Moore law, becausethe Moore law is based on the consideration of 2-dimensional packaging of IC chip.In order to bring out high performance from VLSI chips while restricting their powerconsumption, there are two approaches. One is to reconsider circuits and system architecture fromview point of power consumption. Another is to construct three-dimensional VLSI structure. Inrecent devices, the signal propagation delay is mainly determined by wiring length and pincapacitance. Three-dimensional very large-scale integration (3D-VLSI) is the one solution toimprove performance without increase of power consumption. One of the key issues to realize3D-VLSI is the method of information transfer and the supply of electric power among stackedchips. There are many methods to connect interchip, such as wire-bonding, edge connect, capacitiveor inductive coupling method, and direct contact using through-silicon via (TSV).According to the current reports, TSV seems to be a good candidate to solve the requirement ofmultifunction, high memory capacity, low power consumption and so on. This process technologyneeds absolutely professional electrochemical deposition (ECD) technique. In this work, wepropose three professional ECD techniques, including three specific copper plating formulas, whichcan meet the current demand for TSV metallization. These three copper ECD formulas can result inbottom-up filling of TSV in a flat plane mode, highly selective copper fill, and direct filling ofthrough silicon hole (TSH). Once these copper ECD techniques are successfully developed, thesteps and cost of the TSV process can be significantly reduced. This plan will take two years tocome true, in which electrochemical analyses, in situ electrochemical scanning tunnelingmicroscopy (EC-STM), electrode kinetics, formulation of copper plating, and processesdevelopment of TSV will be employed in this plan. Therefore, this is a complete plan regarding theTSV copper metallization of 3D IC.在過去的 30 年當中，半導體整合技術已經在2 度空間（2D）構裝中廣泛的應用。這樣的技術不但是在電子工業上被廣泛地應用，也在許多相關工業領域上被廣泛地應用，如光電產業、生物機電產業、生醫系統、電子分析、電腦系統、軍事系統、衛星系統、潛艇系統等。從消費性電子到尖端科技產品以及軍事用途上，幾乎所有的工業產品都結合了半導體元件。半導體製程至所以可以如此快速的進展，主要原因之一是MOS 元件具有良好的可尺寸化能力。但是，材料的尺寸是有限的。目前製程能力已經使用銅內連結技術，到達22 奈米。因此，MOS 元件的發展可能將無法再遵守Moore 定律，因為Moore 定律是基於IC 晶片二度空間封裝的考量。為了落實超大型積體電路（VLSI）晶片的高性能，同時還必須限制其電力的消耗，有兩個方式可以進行。一是由電力消耗的觀點，重新考慮線路與系統的架構；另一個方式則是去建構三度空間（3D）的VLSI 結構。在最近的發展的元件當中發現，信號傳遞延遲主要是由線路長度以及引腳電流容量所主導。而3D-VLSI 的結構設計正好可以在不增加電力消耗的條件之下，解決此問題，同時可以大幅提昇元件性能。關鍵性3D-VLSI 的爭議是訊息的傳遞方式與堆疊晶片之間的電力供給，對於此爭議，有許多方法可以來讓晶片互連，例如藉由打線、邊緣連結、電容或電桿結合以及利用穿矽孔（TSV）直接接通等。根據最近的報導，TSV 似乎是很好的候選者，用來解決多功能、高記憶容量以及低耗電量等的需求。這個製程技術需要絕對專業的電化學沈積（ECD）技巧，因此，在此計畫中，吾人提出三個專業的ECD 技術，包含三個特定的電鍍銅配方，這些配方都可以滿足目前TSV金屬化的需求。這三個ECD 銅配方可以產生平面式的孔底上移填充TSV 機制；可以做高度選擇性的填銅以及可以直接填充穿矽通孔（TSH）。一旦這些ECD 銅技術開發成功，TSV 製程的步驟、成本都可以大幅地降低。本計畫預計花兩年的時間來開發，其中會用到電化學分析技術、臨場電化學掃描穿隧顯微鏡、電極動力學、電鍍銅配方開發技術以及TSV 製程技術，對於3D IC 的TSV 銅金屬化製程而言，是相當完整的一套研發計畫

Research and Development of Analysis and Monitoring for Copper Metallization Process

Recently, the features of electronic products tend to lighter, thinner, shorter, and smaller.Therefore, more active IC devices those possess fine conducting lines must be assembled inthe electronic products in order to meet the requirements. So far, the line width of thestate-of-the-art IC chips has shrunk to 45 ~ 65 nm. Hence, aluminum metallization process forinterconnect fabrication of IC chips must be replaced by copper metallization process, that is,Dual Damascene process, which is carried out by copper electrodeposition. To meet therequirement of high I/O counts of advanced IC chip, the microvias those are designed in ICsubstrates and printed circuit boards (PCBs) to serve as interconnect also need to bemetallized by copper electroplating. Consequently, not only the submicron vias of IC chip butalso the microvias of PCB must be fully filled by copper electrodeposition in a mode ofbottom-up filling or superfilling. It has been confirmed that the special electrochemicaldeposition behavior is achieved by interaction of chemical additives and by interactionbetween chemical factors and physical factors. Therefore, this electrochemical copper processis not easily controlled by only analyzing the individual concentration of these additives. Howto monitor the interaction will be a main problem. Accordingly, we plan to develop twoelectrochemical analysis methods those can effectively analyze the concentration of additivesand one electrochemical monitoring method that can effectively quantitatively show thefilling performance of a plating solution. The whole project will be carried out for three years,where the analysis method for determination of accelerator concentration will be carried outin the first year, the analysis method for determination of suppressor concentration will becarried out in the second year, and the method for monitoring filling performance of a platingsolution will be carried out in the last year. The electrochemical principle utilized in theaccelerator analysis is based on a concept of self-assembly monolayer (SAM), the principleutilized in the suppressor analysis is based on the adsorptive mechanism of polyethyleneglycol (PEG), and the principle employed in the monitoring of filling performance is based onthe concept of physicochemical interaction. Within the three years, we shall not only developthe metrology for quantitative analysis but also attempt to fabricate a tool for practical use,especially for on-line usage. If this project could be carried out, this tool designed in this workwill give the copper metallization process a total solution, which can significantly enhance theprocess yield and reduce the process cost.近年來，電子產品之特色傾向於輕薄短小，為了要滿足此項需求，更多具有細導線的主動元件必須被組裝於這些電子產品中。到目前為止，最高階IC 晶片的線寬已經向下縮小到45～65 奈米。因此，IC 晶片的鋁金屬化製程必須被銅金屬化製程，即所謂的由銅電化學沈積所實行的雙鑲嵌製程所取代。為了匹配高階IC 晶片的高I/O 數量之需求，設計在IC 基板以及印刷電路板中，擔負內連接的微米盲孔也需要利用電鍍銅來加以金屬化。所以，不僅是IC 晶片的次微米孔洞而已，PCB 的微米孔洞亦必須要藉由電鍍銅以「孔底上移」或是「超級填充」的模式來予以完全填滿。事實上，文獻報導已經證實，這種特殊的電化學沈積行為是藉由化學添加劑之間的交互作用以及藉由化學因子與物理因子之間的交互作用來完成的。因此，這種電化學銅製程不容易僅藉由分析添加劑的個別濃度來控制。如何監控他的交互作用將是主要的問題。有鑑於此，吾人將計畫開發兩個能有效分析添加劑的電化學分析方法以及一個能有效定量顯示電鍍液之填孔能力的電化學監控方法。整個計畫將費時三年，其中用來決定加速劑濃度的分析方法將於第一年期間完成；用來決定抑制劑濃度的分析方法將於第二年期間完成；用來監控電鍍液之填孔能力的方法將於最後一年來完成。用於加速劑分析的基本原理則是基於單分子層自組裝的觀念來開發；用於抑制劑分析的基本原理則是基於聚乙烯醇的吸附機構來開發；用於監控填孔能力的基本原理則是基於物理化學交互作用的觀念來開發。在這三年期間，吾人不僅將開發定量分析的度量方法，同時亦企圖去組裝一個能實用的器具，特別能於線上使用。若是此計畫能實現，則於計畫中所設計的器具將會帶給銅金屬化製程一個整套解決方案，如此能大幅提昇製程的良率以及降低製程的成本

Microvia Filling by Cu Electroplating Over a Au Seed Layer Modified by a Disulfide

A plating process for microvia filling by Cu electroplating, carried out in a plating bath without an accelerator but with a suppressor only, is proposed in this work. The seed layer of microvia used for subsequent Cu-filling plating is Au formed by electroless plating. The surface of the Au seed layer is modified in a solution containing bis(3-sulfopropyl)-disulfide (SPS) and various supporting electrolytes. This pretreatment is similar to the self-assembly monolayer (SAM) of a thiol molecule on a Au substrate. The coverage density of the adsorbed thiolate strongly depends on the presence or the absence of a supporting electrolyte and it crucially determines the filling performance of the plating process. The plating results demonstrate that the thiolate adlayer which is initially formed on the Au seed layer is transferable onto the surface of the plated Cu and then interacts with chloride ions to further facilitate Cu nucleation and growth. According to the results of the filling plating and the electrochemical analysis, an accelerating mechanism of SPS-SAM for copper electrodeposition and its transferring mechanism are proposed in this work

CHEMICAL METHOD FOR METALLIC NANOPARTICLES GRAFTING

一種奈米金屬的化學接枝方法，將帶有奈米金屬粒子的接枝單元以共價鍵及離子鍵方式與至少另一接枝單元接枝，以固定在基材上，形成化學接枝的奈米金屬

METHOD FOR METALLIZATION OF FLEXIBLE POLYIMIDE FILM

一種軟性基板表面金屬化方法至少包含以下步驟。首先，將聚亞醯胺基板以強鹼溶液處理。接著，利用鎳離子與聚亞醯胺基板進行離子交換。最後，將聚亞醯胺基板浸入含有金屬離子之還原劑溶液中，以於聚亞醯胺基板表面形成奈米鎳金屬層。其中微量金屬離子為選自由鉑族金屬離子與IB族金屬離子所組成之群組

Modification of Cu nanoparticles with a disulfide for polyimide metallization

Copper metallization on polyimide films was carried out via a wet chemical process. This process included the chemical reaction of KOH with PI to form poly(amic acid) (PAA), ion exchange of doped K(+) with Cu(2+) to form Cu(2+)-doped PAA, doped Cu(2+) reduction by aqueous dimethylamine borane (DMAB) to form copper nanoparticles (CNPs) on PAA, and electroless copper (ELC) deposition catalyzed by CNPs on PAA. An organic additive, namely, bis(3-sulfopropyl)-disulfide (SPS), that can effectively reduce the size of CNPs and significantly enhance the chemical activity of CNPs for ELC deposition was used in this work. For comparison, doped Cu(2+) ions in the PAA were also reduced by hydrogen gas at 350 degrees C. The results show that only aqueous reductants can induce the reduced copper atoms to aggregate on the PAA surface and to form a granular copper layer that acts as a catalyst for the ELC deposition. Mechanisms for the aggregation of copper atoms and for activity enhancement of the CNPs due to SPS addition in the DMAB solution are proposed according to the evidence obtained from Fourier transform infrared spectrometry (FTIR), X-ray photoelectron spectrometry (XPS), field emission scanning electron microscopy (FESEM), cross-sectional transmission electron microscopy (TEM), and atomic force microscopy (AFM). The CNP-coated PAA films and the structures of the ELC deposits were characterized by X-ray diffraction (XRD) and UV-visible spectrophotometry (UV-Vis), respectively

Enhancement of filling performance of a copper plating formula at low chloride concentration

In this work, microvia filling was performed by copper electroplating using two plating formulas with and without a leveler at a low concentration of chloride. The base plating solution contained CuSO4, H2SO4, polyethylene glycol (PEG), his (3-sulfopropyl) disulfide (SPS) and Cl-. When the Cl- concentration was lower than 30 ppm, the plating formula without a leveler became dead for bottom-up filling, resulting in conformal deposition. The addition of I ppm Alcian Blue, used as a leveler, could effectively recover the filling performance of the plating formula with low chloride concentration. Electrochemical analyses revealed possible mechanisms. The results demonstrate that the usage of Alcian Blue can widen the operation window of chloride concentration, since it can assist PEG in competing with SPS in adsorption at low chloride concentration. (c) 2008 Elsevier Ltd. All rights reserved

METHOD FOR SYNTHESIS OF METAL NANOPARTICLES

一種奈米金屬粒子之合成方法,其步驟包含選用一摻有金屬離子之固態聚亞醯胺酸,且選用具有一添加劑之一還原液,而將該聚亞醯胺酸置入一還原液中。還原液可將金屬離子還原至聚亞醯胺酸,而還原後的金屬離子可與添加劑產生反應而懸浮於還原液中。藉此,透過前述的異相化學反應可產生均勻粒徑的奈米金屬粒子