Hardware accelerator design for image processing

[[sponsorship]]FIRA Robot World Congress[[conferencetype]]國際[[conferencedate]]20120820~20120822[[conferencelocation]]Bristol, United Kingdo

Hardware/software co-design for particle swarm optimization algorithm

[[abstract]]This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve design flexibility and execution performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a Particle Updating Accelerator module via hardware implementation for updating velocity and position of particles and a Fitness Evaluation module implemented either on a soft-cored processor or Field Programmable Gate Array (FPGA) for evaluating the objective functions are respectively designed to work closely together to carry out the evolution process at different design stages. Thanks to the design flexibility, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To further improve the execution performance of the PSO, a hardware random number generator (RNG) is also designed in this paper in addition to a particle re-initialization scheme to promote exploration search during the optimization process. Experimental results have demonstrated that the proposed HW/SW co-design approach for PSO algorithms has good efficiency for obtaining high-quality solutions for embedded applications.[[incitationindex]]SCI[[booktype]]紙

Hardware Accelerator Design for Image Processing

[[abstract]]This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.[[conferencetype]]國際[[conferencedate]]20120820~20120823[[booktype]]電子版[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]Bristol, U

Humanoid robot transmission chip design

[[conferencetype]]國際[[conferencedate]]20120829~20120831[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]Taipei, Taiwa

Switching-type PD-PI controller design by HEA for AVR system

[[abstract]]In this paper, a switching-type PD-PI controller (SWPD-PI) is proposed and a parameter selection method based on a hybrid evolution algorithm (HEA) is used to select the control parameters effectively for an automatic voltage regulator (AVR) system. The proposed switching-type PD-PI control structure combines improved transient response and reduction of steady state error to produce good global response. In the selections of parameters, HEA is applied to select an appropriate switching value and the control parameters in PD and PI controllers so that the controlled system may have good performance. In the selection of the fitness function, a new evaluation method for system performance is applied so that evolution algorithms can effectively find an appropriate parameter set. Finally, the proposed method is applied in the AVR system. From some simulation and comparison results, we can see that the proposed parameter selection method can effectively find a parameter set for the proposed switching-type PD-PI controller to yield better control performance.[[incitationindex]]SCI[[booktype]]紙本[[booktype]]電子