Power Optimization of Combinational Quaternary Logic Circuits

Design of the binary logic circuits is restricted by the need of the interconnections. Interconnections increase delay, area and energy consumption in CMOS digital circuits. A possible solution could be here at by using a bigger set of signals over the same chip area. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of necessary interconnections. In this paper we design various combinational circuits using quaternary logic. Various combinational circuit such as multi valued logic full adder using unique encoding technique, quaternary encoder and quaternary multiplexer. This design is target to reduce the transistor used to implement the circuit and dropping the power dissipation. Power optimization is achieved using MTCMOS technique. Simulation has been done in Tanner 13 EDA tool on BSIM3 180 nm CMOS Technology. DOI: 10.17762/ijritcc2321-8169.15026