Private-Law Models for Official Immunity

A method for correcting matching errors in an ADC is presented. The method uses the unknown input data from the application and does not require any test signal. Two algorithms for implementing the method are compared. One algorithm is general and works on any type of ADC. The other algorithm utilizes the subranged architecture of a specific ADC and is very simple to implement in hardware. The signal quality is similar for both algorithms

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties;\ud a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design

Fano-ADC(2,2) method for electronic decay rates

Fano-ADC is a family of ab initio methods for prediction of electronic decay widths in excited, singly- and doubly-ionized systems. It has been particularly successful in elucidating the geometry dependence of the inter-atomic decay widths in clusters and facilitated prediction of new electronic decay phenomena. However, the available Fano-ADC schemes are limited to the second order treatment of the initial state and fist-order treatment of the final states of the decay. This confines the applicability of the Fano-ADC approach to first-order decay processes, e.g. normal but not double Auger decay, and compromises the numerical accuracy of the schemes through the unbalanced treatment of electronic correlation. Here we introduce the ADC(2,2) approximation for singly ionized states which describes both initial and final states of the decay up to second order. We use the new scheme to construct the Fano-ADC(2,2) approximation for the decay widths and show that it provides superior accuracy for the decay widths of a series of processes. Moreover, the Fano-ADC(2,2) method provides access to second-order decay processed, such as double Auger decay, which are qualitatively beyond reach of the previously available Fano-ADC implementations.Comment: 41 pages, 4 figure

A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications

This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2nW at 4kS/s and achieves 9.5 ENOB.Ministerio de Economía y Competitividad TEC2012-33634Office of Naval Research (USA) N0001414135

The Infrared Imaging Spectrograph (IRIS) for TMT: the atmospheric dispersion corrector

We present a conceptual design for the atmospheric dispersion corrector (ADC) for TMT's Infrared Imaging Spectrograph (IRIS). The severe requirements of this ADC are reviewed, as are limitations to observing caused by uncorrectable atmospheric effects. The requirement of residual dispersion less than 1 milliarcsecond can be met with certain glass combinations. The design decisions are discussed and the performance of the design ADC is described. Alternative options and their performance tradeoffs are also presented.Comment: SPIE Astronomical Instrumentation 201

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step