5,923 research outputs found
Computing centroids in current-mode technique
A novel current-mode circuit for calculating the centre of mass of a discrete distribution of currents is described. It is simple and compact, an ideal building block for VLSI analogue IC design. The design principles are presented as well as the simulated behaviour of a one-dimensional implementation
Two-phase RTD-CMOS pipelined circuits
MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have been reported using different clock schemes including a four-phase strategy and a single-phase clock scheme. In particular, significant power advantages of single-phase RTD-CMOS MOBILE circuits over pure CMOS have been shown. This letter compares the RTD-CMOS realizations using a single clock and a novel two-phase clock solution. Significant superior robustness and performance in terms of power and area are obtained for the two-phase implementations
A scalable hardware and software control apparatus for experiments with hybrid quantum systems
Modern experiments with fundamental quantum systems - like ultracold atoms,
trapped ions, single photons - are managed by a control system formed by a
number of input/output electronic channels governed by a computer. In hybrid
quantum systems, where two or more quantum systems are combined and made to
interact, establishing an efficient control system is particularly challenging
due to the higher complexity, especially when each single quantum system is
characterized by a different timescale. Here we present a new control apparatus
specifically designed to efficiently manage hybrid quantum systems. The
apparatus is formed by a network of fast communicating Field Programmable Gate
Arrays (FPGAs), the action of which is administrated by a software. Both
hardware and software share the same tree-like structure, which ensures a full
scalability of the control apparatus. In the hardware, a master board acts on a
number of slave boards, each of which is equipped with an FPGA that locally
drives analog and digital input/output channels and radiofrequency (RF) outputs
up to 400 MHz. The software is designed to be a general platform for managing
both commercial and home-made instruments in a user-friendly and intuitive
Graphical User Interface (GUI). The architecture ensures that complex control
protocols can be carried out, such as performing of concurrent commands loops
by acting on different channels, the generation of multi-variable error
functions and the implementation of self-optimization procedures. Although
designed for managing experiments with hybrid quantum systems, in particular
with atom-ion mixtures, this control apparatus can in principle be used in any
experiment in atomic, molecular, and optical physics.Comment: 10 pages, 12 figure
The digital data processing concepts of the LOFT mission
The Large Observatory for X-ray Timing (LOFT) is one of the five mission
candidates that were considered by ESA for an M3 mission (with a launch
opportunity in 2022 - 2024). LOFT features two instruments: the Large Area
Detector (LAD) and the Wide Field Monitor (WFM). The LAD is a 10 m 2 -class
instrument with approximately 15 times the collecting area of the largest
timing mission so far (RXTE) for the first time combined with CCD-class
spectral resolution. The WFM will continuously monitor the sky and recognise
changes in source states, detect transient and bursting phenomena and will
allow the mission to respond to this. Observing the brightest X-ray sources
with the effective area of the LAD leads to enormous data rates that need to be
processed on several levels, filtered and compressed in real-time already on
board. The WFM data processing on the other hand puts rather low constraints on
the data rate but requires algorithms to find the photon interaction location
on the detector and then to deconvolve the detector image in order to obtain
the sky coordinates of observed transient sources. In the following, we want to
give an overview of the data handling concepts that were developed during the
study phase.Comment: Proc. SPIE 9144, Space Telescopes and Instrumentation 2014:
Ultraviolet to Gamma Ray, 91446
The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter
In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution
Clock Distribution Network Building Algorithm For Multiple Ips In System On A Chip
In this project, an algorithm is proposed and developed to build the global CDN
that is used to distribute the clocks to all partitions in the SoC using the channels available
between partitions. The conventional method of building the global CDN involves
manual interventions which decrease the global CDN building efficiency and increase the
overall SoC design cycle. To solve this issue, an algorithm is proposed to automate the
global CDN building process and at the same time obtain a balanced overall CDN not
achieved by the conventional method. Other researches have proposed different CDN
structures to simplify the design process but the proposals often sacrifice placement
resources to achieve this. The algorithm first collects the partition clock latency numbers
and other constraints needed as setup. When the setup is done, the global CDN is build
and routed. The algorithm checks for clock skew and scenic routing issues before
proceeding to shield the global CDN to prevent cross-talk issues. The algorithm is done
when a final checking on the clock skew is done. The algorithm is tested on two different
floorplans with varying size and available channels using three different clocks for each
floorplan to ensure the accuracy of the algorithm. Finally, the global CDN build using the
algorithm is evaluated based on the time needed to build the global CDN and the clock
buffer numbers and areas used. The algorithm is shown to be able to reduce 50% of the
global CDN design cycle and save 5% of clock buffer numbers and areas. The
improvement achieved by the algorithm in this project shows the efficiency in designing
the global CDN improved tremendously compared to conventional method
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