2 research outputs found
Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Enhancement
As capacity and complexity of on-chip cache memory hierarchy increases, the
service cost to the critical loads from Last Level Cache (LLC), which are
frequently repeated, has become a major concern. The processor may stall for a
considerable interval while waiting to access the data stored in the cache
blocks in LLC, if there are no independent instructions to execute. To provide
accelerated service to the critical loads requests from LLC, this work
concentrates on leveraging the additional capacity offered by replacing
SRAM-based L2 with Spin-Transfer Torque Random Access Memory (STT-RAM) to
accommodate frequently accessed cache blocks in exclusive read mode in favor of
reducing the overall read service time. Our proposed technique partitions L2
cache into two STT-RAM arrangements with different write performance and data
retention time. The retention-relaxed STT-RAM arrays are utilized to
effectively deal with the regular L2 cache requests while the high retention
STT-RAM arrays in L2 are selected for maintaining repeatedly read accessed
cache blocks from LLC by incurring negligible energy consumption for data
retention. Our experimental results show that the proposed technique can reduce
the mean L2 read miss ratio by 51.4% and increase the IPC by 11.7% on average
across PARSEC benchmark suite while significantly decreasing the total L2
energy consumption compared to conventional SRAM-based L2 design
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders
Resistive memories have limited lifetime caused by limited write endurance
and highly non-uniform write access patterns. Two main techniques to mitigate
endurance-related memory failures are 1) wear-leveling, to evenly distribute
the writes across the entire memory, and 2) fault tolerance, to correct memory
cell failures. However, one of the main open challenges in extending the
lifetime of existing resistive memories is to make both techniques work
together seamlessly and efficiently. To address this challenge, we propose
WoLFRaM, a new mechanism that combines both wear-leveling and fault tolerance
techniques at low cost by using a programmable resistive address decoder
(PRAD). The key idea of WoLFRaM is to use PRAD for implementing 1) a new
efficient wear-leveling mechanism that remaps write accesses to random physical
locations on the fly, and 2) a new efficient fault tolerance mechanism that
recovers from faults by remapping failed memory blocks to available physical
locations. Our evaluations show that, for a Phase Change Memory (PCM) based
system with cell endurance of 108 writes, WoLFRaM increases the memory lifetime
by 68% compared to a baseline that implements the best state-of-the-art
wear-leveling and fault correction mechanisms. WoLFRaM's average / worst-case
performance and energy overheads are 0.51% / 3.8% and 0.47% / 2.1%
respectively.Comment: To appear in ICCD 202