On the development of memristive devices for electroforming-free and analog memristive crossbar arrays

Memristive devices can reversibly change their resistance by applying an electrical voltage or current. These thin-film devices have the potential to serve as central components in novel neuromorphic circuits, similar to synapses in the human brain. Unlike traditional neuromorphic systems, they enable a state-based and non-volatile weight between two neurons. This comes very close to the natural model of the human brain, where information is stored and processed together. The aim of this thesis was the development of novel memristive devices and the integration into crossbar arrays. An essential requirement was an analogous resistance change, which allows continuous changes in resistance. It was found, that devices with a combination of tunnel and Schottky barriers are best suited for this purpose. These double barrier devices show an analogous and homogeneous resistance change. As a reference system, filament-based memristive devices have been developed that alter their resistance due the migration of silver. Since the formation of filaments is almost random, they have a significantly higher device variability and very few states between the off- and on-state. Only the high quality of the double barrier component allowed the circuit integration without the need to individually adjust circuit parameters for each memristive device. Due to the non-linear switching characteristics and the advantageous I-V characteristics, the devices were integrated into a space-saving crossbar architecture, which increased the packing density tenfold. Due to the simultaneously simplified electrical connection, it was possible to realize a circuit for pattern classification with 180 memristive devices. The construction of an automated measuring system enabled the characterization of a large number of devices. The development of database-supported measurement and evaluation programs facilitated the analysis of the device and switching properties

Organic Bioelectronics Development in Italy: A Review

In recent years, studies concerning Organic Bioelectronics have had a constant growth due to the interest in disciplines such as medicine, biology and food safety in connecting the digital world with the biological one. Specific interests can be found in organic neuromorphic devices and organic transistor sensors, which are rapidly growing due to their low cost, high sensitivity and biocompatibility. This trend is evident in the literature produced in Italy, which is full of breakthrough papers concerning organic transistors-based sensors and organic neuromorphic devices. Therefore, this review focuses on analyzing the Italian production in this field, its trend and possible future evolutions

Cellular Nonlinear Networks: optimized implementation on FPGA and applications to robotics

L'objectiu principal d'aquesta tesi consisteix a estudiar la factibilitat d'implementar un sensor càmera CNN amb plena funcionalitat basat en FPGA de baix cost adequat per a aplicacions en robots mòbils. L'estudi dels fonaments de les xarxes cel•lulars no lineals (CNNs) i la seva aplicació eficaç en matrius de portes programables (FPGAs) s'ha complementat, d'una banda amb el paral•lelisme que s'estableix entre arquitectura multi-nucli de les CNNs i els eixams de robots mòbils, i per l'altre banda amb la correlació dinàmica de CNNs i arquitectures memristive. A més, els memristors es consideren els substituts dels futurs dispositius de memòria flash per la seva capacitat d'integració d'alta densitat i el seu consum d'energia prop de zero. En el nostre cas, hem estat interessats en el desenvolupament d’FPGAs que han deixat de ser simples dispositius per a la creació ràpida de prototips ASIC per esdevenir complets dispositius reconfigurables amb integració de la memòria i els elements de processament general. En particular, s'han explorat com les arquitectures implementades CNN en FPGAs poden ser optimitzades en termes d’àrea ocupada en el dispositiu i el seu consum de potència. El nostre objectiu final ens ah portat a implementar de manera eficient una CNN-UM amb complet funcionament a un baix cost i baix consum sobre una FPGA amb tecnología flash. Per tant, futurs estudis sobre l’arquitectura eficient de la CNN sobre la FPGA i la interconnexió amb els robots comercials disponibles és un dels objectius d'aquesta tesi que se seguiran en les línies de futur exposades en aquest treball.El objetivo principal de esta tesis consiste en estudiar la factibilidad de implementar un sensor cámara CNN con plena funcionalidad basado en FPGA de bajo coste adecuado para aplicaciones en robots móviles. El estudio de los fundamentos de las redes celulares no lineales (CNNs) y su aplicación eficaz en matrices de puertas programables (FPGAs) se ha complementado, por un lado con el paralelismo que se establece entre arquitectura multi -núcleo de las CNNs y los enjambres de robots móviles, y por el otro lado con la correlación dinámica de CNNs y arquitecturas memristive. Además, los memristors se consideran los sustitutos de los futuros dispositivos de memoria flash por su capacidad de integración de alta densidad y su consumo de energía cerca de cero. En nuestro caso, hemos estado interesados en el desarrollo de FPGAs que han dejado de ser simples dispositivos para la creación rápida de prototipos ASIC para convertirse en completos dispositivos reconfigurables con integración de la memoria y los elementos de procesamiento general. En particular, se han explorado como las arquitecturas implementadas CNN en FPGAs pueden ser optimizadas en términos de área ocupada en el dispositivo y su consumo de potencia. Nuestro objetivo final nos ah llevado a implementar de manera eficiente una CNN-UM con completo funcionamiento a un bajo coste y bajo consumo sobre una FPGA con tecnología flash. Por lo tanto, futuros estudios sobre la arquitectura eficiente de la CNN sobre la FPGA y la interconexión con los robots comerciales disponibles es uno de los objetivos de esta tesis que se seguirán en las líneas de futuro expuestas en este trabajo.The main goal of this thesis consists in studying the feasibility to implement a full-functionality CNN camera sensor based on low-cost FPGA device suitable for mobile robotic applications. The study of Cellular Nonlinear Networks (CNNs) fundamentals and its efficient implementation on Field Programmable Gate Arrays (FPGAs) has been complemented, on one side with the parallelism established between multi-core CNN architecture and swarm of mobile robots, and on the other side with the dynamics correlation of CNNs and memristive architectures. Furthermore, memristors are considered the future substitutes of flash memory devices because of its capability of high density integration and its close to zero power consumption. In our case, we have been interested in the development of FPGAs that have ceased to be simple devices for ASIC fast prototyping to become complete reconfigurable devices embedding memory and processing elements. In particular, we have explored how the CNN architectures implemented on FPGAs can be optimized in terms of area occupied on the device or power consumption. Our final accomplishment has been implementing efficiently a fully functional reconfigurable CNN-UM on a low-cost low-power FPGA based on flash technology. Therefore, further studies on an efficient CNN architecture on FPGA and interfacing it with commercially-available robots is one of the objectives of this thesis that will be followed in the future directions exposed in this work

Design, Fabrication, and Characterization of Conjugated Polymeric Electrochemical Memristors as Neuromorphic/Integrated Circuits

Organic materials are promising candidates for future electronic devices compared to the complementing inorganic materials due to their ease of processability, use, and disposal, low cost of fabrication, energy efficiency, and flexible nature toward implementation as flexible and non-conformal devices.With that in mind, electrochemical materials have been widely demonstrated with commercial use as sensors, displays, and a variety of other electronic devices. As Moore\u27s law predicts the increase in the density of transistors on a chip, the requirement to create either smaller transistors or the replacement of the transistor device entirely is apparent. Memory resistors, coined ``memristor , are variable resistive tuning devices that are capable of information processing and data storage in one device. This work focuses on the embodiment of a non-volatile conjugated polymeric electrochemical memristor. Three-terminal memristive systems are fabricated and studied using various electrochemicals (a self-doped PEDOT derivative, a polypyrrole, and a dithienopyrrole derivative) and are tested for their electronic properties and biomimicking capabilities. Optical absorbance properties are studied in order to verify the electrochemical material\u27s redox tuning potential for their respective oxidized and reduced chemical forms. The three-terminal device employed a post-synaptic ``read\u27\u27 channel where conductivity of the electrochemical material was equated to synaptic weight and was electronically decoupled from the pre-synaptic programming electrode by means of a polymeric gel electrolyte. Basic electronic characteristics are exhibited for these three devices such as state stability and retention, non-volatile voltage-driven conductivity tuning, input parameter characteristic trends, and power consumption per input program. Biological synapses consume, on the order of, 1 - 100 fJ of energy per synaptic energy. The electrochemical materials used in this study, at their most optimized input parameters, were capable of demonstrating a 4.16 fJ/mm2 power consumption per input pulse and lead to a promising candidate for implementation as future artificial neural networks. Biological mimicry was displayed for these devices in the form of paired-pulse facilitation and paired-pulse depression, both a form of short term memory which observes the effect the timescale between two incoming inputs has on the change in the final output signal. Toward the indication for the replacement of transistors with three-terminal memristors, basic circuit operations are achieved and demonstrated for these devices. These operations include both Boolean and elementary algebra, key features that demonstrate data processing and storage in-memory where the physical states of the conjugated polymer film represent either logical statements or arithmetic counting variables. The Boolean algebra demonstrated the use of a single memristive device equal to a variety of single logic gates (AND, NAND, OR and NOR) where, by wiring several devices in series, more advanced combinational logic gates can be achieved. Furthermore, each device was capable of displaying elementary algebra for the basic arithmetic functions of addition, subtraction, multiplication, and division. In regards to thin film deposition techniques, the self-doped PEDOT device employed roll-to-roll gravure printing, a high speed and high resolution commercially used deposition technique. The polypyrrole device was fabricated implementing an in-situ polymerization technique, referred to as vapor phase polymerization, and demonstrated the use of this technique toward non-conformal devices. The dithienopyrrole derivative was polymerized through the same vapor phase polymerization technique as the polypyrrole and used in tandem with screen printing in order to construct the final device, including the oxidant film, the silver electrodes, and the polymeric gel electrolyte

Bio-inspired Neuromorphic Computing Using Memristor Crossbar Networks

Bio-inspired neuromorphic computing systems built with emerging devices such as memristors have become an active research field. Experimental demonstrations at the network-level have suggested memristor-based neuromorphic systems as a promising candidate to overcome the von-Neumann bottleneck in future computing applications. As a hardware system that offers co-location of memory and data processing, memristor-based networks represent an efficient computing platform with minimal data transfer and high parallelism. Furthermore, active utilization of the dynamic processes during resistive switching in memristors can help realize more faithful emulation of biological device and network behaviors, with the potential to process dynamic temporal inputs efficiently. In this thesis, I present experimental demonstrations of neuromorphic systems using fabricated memristor arrays as well as network-level simulation results. Models of resistive switching behavior in two types of memristor devices, conventional first-order and recently proposed second-order memristor devices, will be first introduced. Secondly, experimental demonstration of K-means clustering through unsupervised learning in a memristor network will be presented. The memristor based hardware systems achieved high classification accuracy (93.3%) on the standard IRIS data set, suggesting practical networks can be built with optimized memristor devices. Thirdly, implementation of a partial differential equation (PDE) solver in memristor arrays will be discussed. This work expands the capability of memristor-based computing hardware from ‘soft’ to ‘hard’ computing tasks, which require very high precision and accurate solutions. In general first-order memristors are suitable to perform tasks that are based on vector-matrix multiplications, ranging from K-means clustering to PDE solvers. On the other hand, utilizing internal device dynamics in second-order memristors can allow natural emulation of biological behaviors and enable network functions such as temporal data processing. An effort to explore second-order memristor devices and their network behaviors will be discussed. Finally, we propose ideas to build large-size passive memristor crossbar arrays, including fabrication approaches, guidelines of device structure, and analysis of the parasitic effects in larger arrays.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147610/1/yjjeong_1.pd

Controlling Ionic Transport in RRAM for Memory and Neuromorphic Computing Applications

Resistive random-access memory, based on a simple two-terminal device structure, has attracted tremendous interest recently for applications ranging from non-volatile data storage to neuromorphic computing. Resistive switching (RS) effects in RRAM devices originate from internal, microscopic ionic migration and the associated electrochemical processes which modify the materials’ chemical composition and subsequently their electrical and other physical properties. Therefore, controlling the internal ionic transport and redox reaction processes, ideally at the atomic scale, is necessary to optimize the device performance for practical applications with large-size arrays. In this thesis we present our efforts in understanding and controlling the ionic processes in RRAM devices. This thesis presents a comprehensive study on the fundamental understanding on physical mechanism of the ionic processes and the optimization of materials and device structures to achieve desirable device performance based on theoretical calculations and experimental engineering. First, I investigate the electronic structure of Ta2O5 polymorphs, a resistive switching material, and the formation and interaction of oxygen vacancies in amorphous Ta2O5, an important mobile defect responsible for the resistive switching process, using first-principles calculations. Based on the understanding of the fundamental properties of the switching material and the defect, we perform detailed theoretical and experimental analyses that reveal the dynamic vacancy charge transition processes, further helping the design and optimization of the oxide-based RRAM devices. Next, we develop a novel structure including engineered nanoporous graphene to control the internal ionic transport and redox reaction processes at the atomic level, leading to improved device performance. We demonstrate that the RS characteristics can be systematically tuned by inserting a graphene layer with engineered nanopores at a vacancy-exchange interface. The amount of vacancies injected in the switching layer and the size of the conducting filaments can be effectively controlled by the graphene layer working as an atomically-thin ion-blocking material in which ionic transports/reactions are allowed only through the engineered nanosized openings. Lastly, better incremental switching characteristics with improved linearity are obtained through optimization of the switching material density. These improvements allow us to build RRAM crossbar networks for data clustering analysis through unsupervised, online learning in both neuromorphic applications and arithmetic applications in which accurate vector-matrix multiplications are required. We expect the optimization approaches and the optimized devices can be used in other machine learning and arithmetic computing systems, and broaden the range of problems RRAM based network can solve.PHDMaterials Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/146119/1/jihang_1.pd

Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing

Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end of CMOS technology scaling, innovations are required to tackle the challenges in a radically different way. Inspired by the emerging understanding of the computing occurring in a brain and nanotechnology-enabled biological plausible synaptic plasticity, neuromorphic computing architectures are being investigated. Such a neuromorphic chip that combines CMOS analog spiking neurons and nanoscale resistive random-access memory (RRAM) using as electronics synapses can provide massive neural network parallelism, high density and online learning capability, and hence, paves the path towards a promising solution to future energy-efficient real-time computing systems. However, existing silicon neuron approaches are designed to faithfully reproduce biological neuron dynamics, and hence they are incompatible with the RRAM synapses, or require extensive peripheral circuitry to modulate a synapse, and are thus deficient in learning capability. As a result, they eliminate most of the density advantages gained by the adoption of nanoscale devices, and fail to realize a functional computing system. This dissertation describes novel hardware architectures and neuron circuit designs that synergistically assemble the fundamental and significant elements for brain-inspired computing. Versatile CMOS spiking neurons that combine integrate-and-fire, passive dense RRAM synapses drive capability, dynamic biasing for adaptive power consumption, in situ spike-timing dependent plasticity (STDP) and competitive learning in compact integrated circuit modules are presented. Real-world pattern learning and recognition tasks using the proposed architecture were demonstrated with circuit-level simulations. A test chip was implemented and fabricated to verify the proposed CMOS neuron and hardware architecture, and the subsequent chip measurement results successfully proved the idea. The work described in this dissertation realizes a key building block for large-scale integration of spiking neural network hardware, and then, serves as a step-stone for the building of next-generation energy-efficient brain-inspired cognitive computing systems