A PROPOSED DUAL SIZE DESIGN FOR ENERGY MINIMIZATION IN SUB-THRESHOLD CIRCUITS

Sub-threshold operation has received a lot of attention in limited performance applications.However, energy optimization of sub-threshold circuits should be performed with the concern of the performance limitation of such circuit. In this paper, a dual size design is proposed for energy minimization of sub-threshold CMOS circuits. The optimal downsizing factor is determined and assigned for some gates on the off-critical paths to minimize the energy at the maximum allowable performance. This assignment is performed using the proposed slack based genetic algorithm which is a heuristic-mixed evolutionary algorithm. Some gates are heuristically assigned to the original and the downsized design based on their slack time determined by static timing analysis. Other gates are subjected to the genetic algorithm to perform an optimal downsizing assignment taking into account the previous assignments. The algorithm is applied for different downsizing factors to determine the optimal dual size for low energy operation without a performance degradation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74283, 74L85, ALU74181, and 16 bit ripple carry adder. The proposed design shows an energy per cycle saving ranged from (29.6% to 56.59%) depending on the utilization of available slack time from the off-critical paths