Efficient Pipelining for Modular Multiplication Architectures in Prime Fields

This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation of the Montgomery algorithm, a more compact pipelined version is derived. The design makes use of 16bit integer multiplication blocks that are available on recently manufactured FPGAs. The critical path is optimized by omitting the exact computation of intermediate results in the Montgomery algorithm using a 6-2 carry-save notation. This results in a high-speed architecture, which outperforms previously designed Montgomery multipliers. Because a very popular application of Montgomery multiplication is public key cryptography, we compare our implementation to the state-of-the-art in Montgomery multipliers on the basis of performance results for 1024-bit RSA

Very High Radix Scalable Montgomery Multipliers

This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Koç scalable architecture using w × v – bit integer multipliers in place of AND gates. The new design can perform 1024-bit modular exponentiation in 6.6 ms using 2847 4-input lookup tables and 32 16 x 16 multipliers, making it the fastest scalable design yet reported. 1

Parallelized Very High Radix Scalable Montgomery Multipliers

Abstract — This paper describes a parallelized very high radix scalable Montgomery multiplier designed for non-redundant FPGA implementations. It improves on the very high radix scalable architecture by using techniques to parallelize the two multiplications within each processing element. The new design can perform 1024-bit modular exponentiation in 5.0 ms and 256bit modular exponentiation in 0.20 ms using 2593 4-input lookup tables and 32 16 × 16 multipliers, improving the fastest scalable design yet reported. I