Vector ISA Extension for Sparse Matrix-Vector Multiplication

. In this paper we introduce a vector ISA extension to facilitate sparse matrix manipulation on vector processors (VPs). First we introduce a new Block Based Compressed Storage (BBCS) format for sparse matrix representation and a Block-wise Sparse Matrix-Vector Multiplication approach. Additionally, we propose two vector instructions, Multiple Inner Product and Accumulate (MIPA) and LoaD Section (LDS), specially tuned to increase the VP performance when executing sparse matrix-vector multiplications. 1 Introduction In many areas of scientific computing the manipulation of sparse matrices constitutes the kernel of the solvers. Improving the e#ciency of sparse operations such as Sparse Matrix-Vector Multiplication (SMVM) has been and continues to be an important research topic. Several compressed formats for sparse matrix representation [5] and algorithms to improve sparse matrix multiplication performance on parallel [3] and vector machines [4] have been developed. Moreover sparse matr..