VLSI ARCHITECTURE AND FPGA IMPLEMENTATION OF ICE ENCRYPTION ALGORITHM

In modern security, the need for safe cryptographic algorithms that are hardware implemental is great. A hardware architecture is proposed in this paper, for the implementation of the ICE encryption algorithm. Since this cipher is optimized for use on software, a hardware implementation of that algorithm that achieves good performance results has much interest. The proposed implementation can be used for both encryption and decryption process. It is a folded architecture using feedback logic, designed for small chip covered area and high speed performance. The proposed architecture was implemented by using an FPGA device. The achieved throughput is equal to 116 Mbit/sec, using a system clock with frequency up to 29.1 MHz. 1