Obtaining functionally equivalent simulations using VHDL and a time-shift transformation

The advent of VHDL has brought about a number of VHDL simulators. Many translation schemes from domain specific languages to supposedly functionally equivalent VHDL have been developed as an approach to obtaining simulations. However, functionally equivalent VHDL can not be created for the general case, due to a theoretical limitation to this approach. It is a very subtle point and has thus been overlooked until now, but it is extremely important since it can cause incorrect siniulation, therefore making translations to VHDL an unsound simulation technique. In this paper, we introduce this fundamental limitation. In addition, we propose an alternative approach which strives for functionally equivalent simulation rather than functionally equivalent VHDL, while still taking advantage of VHDL simulators. Our method uses a novel time-shift transformation, also introduced in this paper, in conjunction with almost any translation scheme. The method makes correct simulations easily obtainable, thus bridging the gap to a truly sound and highly advantageous use of VHDL as a tool for simulating domain specific languages

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

VHDL synthesis system (VSS) : user's manual, version 5.0

This report provides instructions for installing and using the VHDL Synthesis System (Version 5.0). VSS is a high level synthesis sytem that synthesizes structures from an abstract description, written with VHDL behavioral constructs. The system uses components from a generic component library (GENUS). The output of VSS is in structural VHDL and could be verified using a commercial VHDL simulator. The designer can control the synthesis process by providing different resource constraints to the system. VSS is also capable of producing different architectures which can be selected by the designer

Semantics and synthesis of signals in behavioral VHDL

Signals are a fundamental part of VHDL behavioral descriptions. There are many kinds of VHDL signals, each possesing complex and hence often misunderstood semantics. The result is that synthesis tools often inadequately address synthesis of signals. In this report, we first make clear the semantics of the various signal kinds shared by multiple processes through the use of conceptual hardware, rather than just text. Second, with the semantics firmly understood, we discuss techniques and issues in synthesizing actual hardware for shared signals. This information can be used to take a step towards synthesizing correct hardware from VHDL descriptions while greatly reducing current restrictions imposed by synthesis tools on allowable VHDL behavior

Structured modeling for VHDL synthesis

This report will describe a proposed modeling style for the use of the VHSIC Hardware Description Language (VHDL) in design synthesis. We will describe the operations and underlying assumptions of four design models currently understood and used in practice by designers: combinational logic, functional descriptions (involving clocked components such as counters), register transfer (data path) descriptions, and behavioral (instruction set or processor) designs. We will illustrate the various uses of the VHDL description styles (structural, dataflow and behavioral) to represent characteristics of each of these design models. Emphasis is placed on how VHDL constructs should be used in order to synthesize optimal designs

Incorporating VHDL signal/wait semantics into synthesis

VHDL signals and wait statements provide great expressive power for behavioral descriptions. However, due to their simulation semantics, most high-level synthesis tools do not handle these constructs and severely restrict their use, eliminating much of their power. In this report, we introduce a set of transformations to convert signals and wait statements to equivalent constructs that are easily handled by high-level synthesis tools. They greatly enlarge the synthesizable VHDL subset, thus increasing the usefulness and practicality of the language as an input to high-level synthesis. These transformations can also serve as a basis for converting a VHDL process to a form suitable for generation of software

Identification and Characterization of the Lipid Transport System in the Tarantula Grammostola rosea

Lipids due to its hydrophobic nature are transported in the hemolymph mainly by lipoproteic fractions. In the present work we studied the lipoproteic fractions present in the hemolymph of the spider Grammostola rosea. Through ultracentrifugation two lipoproteic fractions are isolated, one of high density named Gr-HDL (δ = 1.13 - 1.15 g/ml) and the other of very high density called Gr-VHDL (δ = 1.24 - 1.27 g/ml) Gr-VHDL in hemolymph is majority in relation to Gr-HDL. In this sense Gr-VHDL fraction has 98.6% of hemolymphatic proteins, and 89.3% of lipids presents in the hemolymph. Both lipoproteic fractions possess phospholipids such as majority lipids (phosphatidylcholine and phosphatidylethanolamine) and 18:1, 16:0, 18:2 and 18:0 as the major fatty acids. In order to confirm the role played by lipoproteic fractions in vitro assays with different 14C-lipid were performed. It was observed that Gr-VHDL takes up mainly free fatty acids and triacylglycerols unlike that observed for Gr-HDL in relation to phosphatidylcholine. Through electrophoresis it was observed that Gr-VHDL has three proteins: a predominant band of 68 kDa and two others of 99 and 121 kDa. Gr-HDL displayed a predominant band of 93 kDa, and other minority of 249 kDa. In conclusion, this study reports lipid characterization of the lipoproteic fractions present in the hemolymph of the tarantula, G. rosea. The role of each lipoproteic fraction in relation to lipid up- take is sustained by in vitro assays. Similarities and differences are found when it is compared to lipoproteins of only the three species of spiders studied.Fil: Laino, Aldana. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones Bioquímicas de La Plata ; ArgentinaFil: Cunningham, Monica Liliana. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones Bioquímicas de La Plata ; ArgentinaFil: Suarez, Gustavo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones Bioquímicas de La Plata ; ArgentinaFil: Garcia, Carlos Fernando. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones Bioquímicas de La Plata ; Argentin

Energy Detection UWB Receiver Design using a Multi-resolution VHDL-AMS Description

Ultra Wide Band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent approaches for the design of the receiver based on energy detection schemes seem suitable to this aim and have been adopted in the project the preliminary results of which are reported in this paper. The objective is the design of a UWB receiver with a top-down methodology, starting from Matlab-like models and refining the description down to the final transistor level. This goal will be achieved with an integrated use of VHDL for the digital blocks and VHDL-AMS for the mixed-signal and analog circuits. Coherent results are obtained using VHDL-AMS and Matlab. However, the CPU time cost strongly depends on the description used in the VHDL-AMS models. In order to show the functionality of the UWB architecture, the receiver most critical functions are simulated showing results in good agreement with the expectations

VSS : a VHDL synthesis system

This report describes a register transfer synthesis system that allows a designer to interact with the design process. The designer can modify the compiled design by changing the input description, selecting optimization and mapping strategies, or graphically changing the generated design schematic. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization. The compilation process consists of two phases. First, a design composed of generic components is synthesized from the input description. Second, this design is translated into components from a particular library by a mapper and optimized by a logic optimizer. Redesign to new technologies can be accomplished by changing only the component library