Utility Optimal Thread Assignment and Resource Allocation in Distributed Systems

Achieving high performance in many distributed systems, such as a web hosting center or the cloud requires finding a good assignment of worker threads to servers and also effectively allocating each server's resources to its assigned threads. The assignment and allocation components of this problem have been studied extensively but largely separately in the literature. In this paper, we introduce the \emph{assign and allocate (AA)} problem, which seeks to simultaneously find an assignment and allocation that maximizes the total utility of the threads. Assigning and allocating the threads together can result in substantially better overall utility than performing the steps separately, as is traditionally done. We model each thread by a utility function giving its utility as a function of its assigned resources. We first prove that the AA problem is NP-hard. We then present a $2 (\sqrt{2}-1) > 0.828$ factor approximation algorithm for concave utility functions, which runs in $O(mn^2 + n (\log mC)^2)$ time for $n$ threads and $m$ servers with $C$ amount of resource each. We further present a faster algorithm with the same approximation ratio and lower time complexity of $O(n (\log mC)^2)$. We then extend our algorithms to solve AA problem with nonconcave utility functions and achieve an approximation ratio $\frac{1}{2}$. We conduct extensive experiments to test the performance of our algorithms on threads with both synthetic and realistic utility functions, and find that it achieves over 92\% of the optimal utility on average. We also compare our algorithm against several other assignment and allocation algorithms, and find that it achieves up to 9 times better total utility.Comment: 15 page

Extreme Software Defined Radio -- GHz in Real Time

Software defined radio is a widely accepted paradigm for design of reconfigurable modems. The continuing march of Moore's law makes real-time signal processing on general purpose processors feasible for a large set of waveforms. Data rates in the low Mbps can be processed on low-power ARM processors, and much higher data rates can be supported on large x86 processors. The advantages of all-software development (vs. FPGA/DSP/GPU) are compelling: much wider pool of talent, lower development time and cost, and easier maintenance and porting. However, very high-rate systems (above 100 Mbps) are still firmly in the domain of custom and semi-custom hardware (mostly FPGAs). In this paper we describe an architecture and testbed for an SDR that can be easily scaled to support over 3 GHz of bandwidth and data rate up to 10 Gbps. The paper covers a novel technique to parallelize typically serial algorithms for phase and symbol tracking, followed by a discussion of data distribution for a massively parallel architecture. We provide a brief description of a mixed-signal front end and conclude with measurement results. To the best of the author's knowledge, the system described in this paper is an order of magnitude faster than any prior published result.Comment: Accepted to 2020 IEEE Aerospace Conferenc