1 research outputs found
A Unified Model for Gate Level Propagation Analysis
Classic hardware verification techniques (e.g., X-propagation and
fault-propagation) and more recent hardware security verification techniques
based on information flow tracking (IFT) aim to understand how information
passes, affects, and otherwise modifies a circuit. These techniques all have
separate usage scenarios, but when dissected into their core functionality,
they relate in a fundamental manner. In this paper, we develop a common
framework for gate level propagation analysis. We use our model to generate
synthesizable propagation logic to use in standard EDA tools. To justify our
model, we prove that Precise Hardware IFT is equivalent to gate level
X-propagation and imprecise fault propagation. We also show that the difference
between Precise Hardware IFT and fault propagation is not significant for
74X-series and '85 ISCAS benchmarks with more than 313 gates and the difference
between imprecise hardware IFT and Precise Hardware IFT is almost always
significant regardless of size