Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints

This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with bandwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints. Keywords: multi-clock domain, wrapper design, SoC, embedded core test, test scheduling