Use of scanning capacitance microscopy for controlling wafer processing

Scanning capacitance microscopy and electrostatic force microscopy have been used to characterize commercial semiconductor devices at various stages of the fabrication process. These methods, combined with conventional atomic force microscopy, allow to visualize qualitatively the oxide thickness, the nature of dopants and the exact position of implanted areas. (C) 2002 Elsevier Science Ltd. All rights reserved

Noncontact electrical metrology of Cu/low-k interconnect for semiconductor production wafers

We have demonstrated a technique capable of in-line measurement of dielectric constant of low-k interconnect films on patterned wafers utilizing a test key of ~50x50 \mu m in size. The test key consists of a low-k film backed by a Cu grid with >50% metal pattern density and <250 nm pitch, which is fully compatible with the existing dual-damascene interconnect manufacturing processes. The technique is based on a near-field scanned microwave probe and is noncontact, noninvasive, and requires no electrical contact to or grounding of the wafer under test. It yields <0.3% precision and 2% accuracy for the film dielectric constant

Establishment of surface functionalization methods for spore-based biosensors and implementation into sensor technologies for aseptic food processing

Aseptic processing has become a popular technology to increase the shelf-life of packaged products and to provide non-contaminated goods to the consumers. In 2017, the global aseptic market was evaluated to be about 39.5 billion USD. Many liquid food products, like juice or milk, are delivered to customers every day by employing aseptic filling machines. They can operate around 12,000 ready-packaged products per hour (e.g., Pure-Pak® Aseptic Filling Line E-PS120A). However, they need to be routinely validated to guarantee contamination-free goods. The state-of-the-art methods to validate such machines are by means of microbiological analyses, where bacterial spores are used as test organisms because of their high resistance against several sterilants (e.g., gaseous hydrogen peroxide). The main disadvantage of the aforementioned tests is time: it takes at least 36-48 hours to get the results, i.e., the products cannot be delivered to customers without the validation certificate. Just in this example, in 36 hours, 432,000 products would be on hold for dispatchment; if more machines are evaluated, this number would linearly grow and at the end, the costs (only for waiting for the results) would be considerably high. For this reason, it is very valuable to develop new sensor technologies to overcome this issue. Therefore, the main focus of this thesis is on the further development of a spore-based biosensor; this sensor can determine the viability of spores after being sterilized with hydrogen peroxide. However, the immobilization strategy as well as its implementation on sensing elements and a more detailed investigation regarding its operating principle are missing. In this thesis, an immobilization strategy is developed to withstand harsh conditions (high temperatures, oxidizing environment) for spore-based biosensors applied in aseptic processing. A systematic investigation of the surface functionalization’s effect (e.g., hydroxylation) on sensors (e.g., electrolyte-insulator semiconductor (EIS) chips) is presented. Later on, organosilanes are analyzed for the immobilization of bacterial spores on different sensor surfaces. The electrical properties of the immobilization layer are studied as well as its resistance to a sterilization process with gaseous hydrogen peroxide. In addition, a sensor array consisting of a calorimetric gas sensor and a spore-based biosensor to measure hydrogen peroxide concentrations and the spores’ viability at the same time is proposed to evaluate the efficacy of sterilization processes

Growth and Characterizations of Silicon nitride thin films on Silicon substrates

Silicon nitride thin films were prepared on Silicon p-type substrates using chemical vapor deposition method. Three Silicon nitride samples were taken. One was not annealed while the rest two were annealed at different temperatures. The films are of 250 nm. Two Si3N4 samples were annealed at 800 oC and 1000 oC in a furnace in the presence of N2. The samples morphological characterizations are done using XRD and SEM. And electrical characterizations are done using C-V. XRD and SEM confirmed its amorphous nature. Electrical properties were found out by capacitance-voltage measurement (C-V)

Formation and characterization of n/p shallow junctions in sub-micron MOSFETs

Semiconductors are the burgeoning industries in today\u27s information age. Silicon based microelectronic devices are shrinking day-by-day in accord with the scaling dimensions reported by the International Technology Roadmap for Semiconductors (ITRS). There have been many semiconductor models and simulation programs constantly keeping pace with the continuously evolving scaling dimensions, process technology, performance and cost. Electrical characterization plays a vital role in determining the electrical properties of materials and device structures. Silicon based Metal Oxide Semiconductor Field Effect Transistor (MOSFET) forms the basis of Complimentary Metal Oxide Semiconductor (CMOS) circuits. Today\u27s aggressive scaling approaches in silicon Integrated Circuit (IC) technology require ultra shallow junctions in MOSFETs. The objective of this thesis is to study the leakage current in n/p shallow junctions and to correlate them with process steps required for the formation of shallow junctions. The leakage current measurements were performed by utilizing three-point probe method, which is one of the popular techniques used in the semiconductor industry. Apart from n/p shallow junctions, experiments have been performed on p/n shallow junctions. Finally, comparison of the leakage current measurements has been made. The comparison takes into account the implant variables and post-implant annealing steps that have been deployed in the fabrication of shallow junctions

Moving towards high carrier mobility power devices in silicon and silicon carbide

This thesis reports on recent progress regarding the characterization, design and fabrication of modern power semiconductor devices in Silicon (Si) as well as in the promising wide band gap material Silicon Carbide (SiC). Up to now, state of the art power devices are architectured on the basis of monocrystalline Si-wafers. This is due to the high material quality of Si in combination with the availability of a mature and reliable fabrication technology based on a well-established process library. However, more and more sophisticated device designs such as e.g. the Super-Junction (SJ) architecture require an increasing number of fabrication steps therefore increasing the amount of possible sources of error. Further, more complex three-dimensional dopant distribution profiles are needed for the devices to withstand the high blocking voltage demands of current power semiconductor applications when operated in reverse direction. This dopant distribution has to be monitored, at least for control samples, after implantation, after further thermal processes and during the duty cycle. To ensure reliable device operation, in particular for charge compensated devices, this monitoring or mapping has to be performed locally with high precision and sensitivity. In this work complementary Scanning Probe Microscopy (SPM) based methods like: Kelvin Probe Force Microscopy (KPFM), Scanning Capacitance Force Microscopy (SCFM) and Scanning Spreading Resistance Microscopy (SSRM) have been explored for a precise monitoring of carrier concentration profiles. This is due to the fact that so far none of the established industrial techniques such as e.g. Secondary Ion Mass Spectrometry (SIMS) or Spreading Resistance Probe (SRP) was mature enough to simultaneously full-fill all the major requirements of the semiconductor industry in terms of spatial resolution, sensitivity, reproducibility and the ability to quantify dopant concentrations. Further, SIMS is probing the chemical composition rather than the charge carrier distribution. To ‘look inside’ the inhomogeneously doped sample, smooth device cross-sections need to be prepared in a reliable manner and without distorting the ‘as implanted/activated’ dopant profile. In this way artefacts arising from a topographic signal can be ruled out. For Si the easiest way would be to cleave the wafer along a certain crystallographic direction. However, since the SPM methods presented here shall serve as a characterization tool with a general validity another approach that is also suitable for different crystal structures and materials with a hardness close to diamond had to be found. For this reason a chemical mechanical polishing (CMP) procedure had been developed at PSI. This process was optimized for maintaining a low surface state density as it is important to avoid a complete pinning of the Fermi level for the KPFM measurements. The subsequent Atomic Force Microscopy (AFM) imaging has been performed in collaboration with the experts in the research group of Prof. Ernst Meyer at the University of Basel. Within this project it has been demonstrated that every SPM derived method is capable to qualitatively map carrier concentrations down to an unprecedented low regime. However, a difference regarding the lateral resolution was observed which can be understood by different information depths depending on the underlying physical quantity to be measured together with an imperfect surface preparation which is leading to an accumulation or depletion of defects at the surface. The most critical technique in that sense - due to its high surface sensitivity - is the contact potential difference measurement that is utilized by KPFM to draw conclusions on the carrier concentration. By laser illumination of the sample during the KPFM experiment a Surface Photo Voltage (SPV) occurs in a surface near layer with a thickness in the order of the minority carrier diffusion length. Thus, the surface sensitivity is reduced and the signal distortion due to the unfavourable influence of surface defects gets less pronounced. Even though SCFM is also based on the detection of the electrostatic force that develops between the tip and the sample, this method is less affected by the surface because it is probing a different physical quantity, namely the total capacitance of the rather extended oxide/depletion layer capacitance system. Furthermore, the magnitude of the SCFM signal scales inverse proportionally with respect to the carrier concentration, hence this method is theoretically offering the highest sensitivity in the low concentration regime. Nevertheless, a quantification scheme for this technique is still in development and further work on locally acquired spectroscopic capacitance-voltage (C-V ) measurements is needed towards a reliable quantification procedure. The third SPM derived method SSRM, is operated in contact mode under high normal forces to ensure that the spreading resistance is the dominant resistance contribution for the current flowing between the tip and the sample. Under these circumstances the local carrier concentration and its impact on the magnitude and the sign of the output current can be investigated in a very accurate and quantitative manner. Beside that, the high mechanical forces cause an abrasive motion of the tip while scanning the sample. This feature is beneficial in two ways: on one hand the native oxide and the underlying defect-rich surface layer are removed while on the other hand a phase transformation of a tiny sample volume just below the tip occurs which locally decreases the resistivity and increases the spatial resolution. Hence, the SSRM technique is showing a high degree of reproducibility and is therefore ideal for quantitative studies. As mentioned above the considerable complexity of the fabrication process and the limited material properties of Si in terms of a high critical electric field and a high thermal conductivity accelerated the search for novel substrates for power semiconductor applications. Beside offering an order of magnitude higher critical electric field due to its wide band gap (WBG), SiC also attracted attention since it can be thermally oxidized resulting in a silicon dioxide (SiO2) layer as its native oxide. Therefore, this material has been classified as most promising and theoretical improvements of a - by a factor of 400 - lower ON-resistance have been calculated. However, to date SiC devices are facing other problems related to the engineering of dopant profiles and the more complex nature of the oxidation process which limit their performance and hinder their large-scale commercialization. The incorporation of a specific dopant distribution in SiC is most effectively done by an ion implantation process followed by a high temperature annealing step which is needed to restore the crystal structure after implantation-induced damage and to electronically activate the dopant atoms. This is caused by the fact that in SiC due to its wide band gap of 2.4-3.2 eV (depending on its poly-type) basically no dopant diffusion at reasonable thermal budgets occurs. Notably, not all of these dopant atoms are ionized and contribute to the electric conduction within the semiconductor. Especially the hole concentration p and the acceptor concentration NA can differ significantly in SiC due to the large ionization energies. Hence it has to be taken into account that the final performance of a SiC power device might be inferior to the expected performance from the implantation parameters. This behaviour is in clear contrast to Si where at room temperature basically all donor and acceptor atoms are ionized and no further differentiation between the dopant and the carrier (electronically active dopant) profile has to be made. The above mentioned SPM methods are sensitive to the carrier rather than to the dopant profile and within this work it has been demonstrated that e.g. the p-doped guard ring structure of a SiC Schottky diode which is shielding the metal contact from high electric fields that occur under reverse bias operation can be resolved. Another challenge for SiC Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are low carrier mobilities inside the thin conducting channel at the semiconductor/oxide interface and threshold voltage instabilities. Due to the more complex nature of the oxidation process which requires the removal of carbon atoms in the form of CO or CO2 from the SiC crystal the SiC/SiO2 interface is showing a high density of interface trap states that act as scattering centres and degrade the carrier mobility. Hence, experimentally observed charge carrier mobilities are by a factor of 10 below the theoretical value of the bulk material. Thereby the ON-resistance which is inverse proportional to the mobility is increased which is leading to a higher amount of power dissipation in the ON-state of the device. Unsurprisingly, a lot of research effort has been triggered in this direction resulting in breakthrough called post-oxidation annealing (POA) under gaseous ambients. Nitrogen and phosphorous based chemistries have shown a passivating effect on the density of interface trap states. However, the origin of this mechanism is not yet fully understood. A possible explanation is a counter-doping effect within a thin layer at the semiconductor surface. A second - maybe easier - pathway to increase the channel mobility is the utilization of the crystal anisotropy. The mobility strongly depends on the orientation of the channel with respect to the crystallographic axis. Among them the 1120 direction exhibits the highest mobility. In the here presented project this approach has been utilized to improve the device performance without changing too many parameters regarding the oxidation or post-oxidation treatments at the same time. In this case the remaining challenge was to develop an etching process which is able to etch several um deep trenches into SiC and to precisely control the shape of the resulting trench profile. It has been demonstrated that sharp corners that would cause field crowding at the edges can be eliminated by the usage of very small DC biases applied between the electrode of the plasma chamber and the substrate. Furthermore, the steepness of the sidewalls could be controlled by the composition of the plasma gas flows. Contrary to previous reports we found that the addition of oxygen to the dry etching process is not helping to avoid microtrenching. Either a pure SF6 based process or an SF6 based process with the addition of Ar have shown the best results. With this success a full manufacturing cycle for a nanoscale trench MOSFET has been designed