5 research outputs found

    Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic

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    In this paper, two circuit topologies of pW-power Hz-range wake-up oscillators for sensor node applications are presented. The proposed circuits are based on standard cells utilizing the Dynamic Leakage Suppression logic style [4]-[5]. The proposed oscillators exhibit low supply voltage sensitivity over a wide supply voltage range, from nominal voltage down to the deep sub-threshold region (i.e., 0.3V). This enables direct powering from energy harvesters or batteries through their whole discharge cycle, suppressing the need for voltage regulation. Post-layout time-domain simulations of the proposed oscillators in 180nm show a power consumption of 1.4-1.7pW, a supply-sensitivity of 55-40%/V over the 0.3V-1.8V supply voltage range, and a compact area down to 1,500μm2. The very low power consumption makes the proposed circuits very well suited for energy-harvested systems-on-chip for Internet of Things applications

    A pW-Power Hz-Range Oscillator Operating With a 0.3-1.8-V Unregulated Supply

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    In this paper, a pW-power relaxation oscillator for sensor node applications is presented. The proposed oscillator operates over a wide supply voltage range from nominal down to deep sub-threshold and requires only a sub-pF capacitor for Hz-range output frequency. A true pW-power operation is enabled thanks to the adoption of an architecture leveraging transistor operation in super-cutoff, the elimination of voltage regulation, and current reference. Indeed, the oscillator can be powered directly from highly variable voltage sources (e.g., harvesters and batteries over their whole charge/discharge cycle). This is achieved thanks to the wide supply voltage range, the low voltage sensitivity of the output frequency and the current drawn from the supply. A test chip of the proposed oscillator in 180 nm exhibits a nominal frequency of approximately 4 Hz, a supply voltage range from 1.8 V down to 0.3 V with 10%/V supply sensitivity, 8-18-pA current absorption, and 4%/°C thermal drift from -20 °C to 40 °C at an area of 1600 μm². To the best of the authors' knowledge, the proposed oscillator is the only one able to operate from sub-threshold to nominal voltage

    Ultra Low-Energy Relaxation Oscillator With 230 fJ/cycle Efficiency

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    Energy-Efficient Circuit Designs for Miniaturized Internet of Things and Wireless Neural Recording

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    Internet of Things (IoT) have become omnipresent over various territories including healthcare, smart building, agriculture, and environmental and industrial monitoring. Today, IoT are getting miniaturized, but at the same time, they are becoming more intelligent along with the explosive growth of machine learning. Not only do IoT sense and collect data and communicate, but they also edge-compute and extract useful information within the small form factor. A main challenge of such miniaturized and intelligent IoT is to operate continuously for long lifetime within its low battery capacity. Energy efficiency of circuits and systems is key to addressing this challenge. This dissertation presents two different energy-efficient circuit designs: a 224pW 260ppm/°C gate-leakage-based timer for wireless sensor nodes (WSNs) for the IoT and an energy-efficient all analog machine learning accelerator with 1.2 µJ/inference of energy consumption for the CIFAR-10 and SVHN datasets. Wireless neural interface is another area that demands miniaturized and energy-efficient circuits and systems for safe long-term monitoring of brain activity. Historically, implantable systems have used wires for data communication and power, increasing risks of tissue damage. Therefore, it has been a long-standing goal to distribute sub-mm-scale true floating and wireless implants throughout the brain and to record single-neuron-level activities. This dissertation presents a 0.19×0.17mm2 0.74µW wireless neural recording IC with near-infrared (NIR) power and data telemetry and a 0.19×0.28mm2 0.57µW light tolerant wireless neural recording IC.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169712/1/jongyup_1.pd
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