The Design and Verification of a Synchronous First-In First-Out (FIFO) Module Using System Verilog Based Universal Verification Methodology (UVM)

With the conventional directed testbench, it is highly improbably to handle verification of current complex Integrated Circuit (IC) designs, because a person has to manually create every test case. The greater the complexity of the designs, the higher the probability of bugs appearing in the code. Increasing complexity of ICs has created a necessity for performing verification on designs with an advanced, automated verification environment. Ideally this would eliminate chip re-spins, minimizing the time required to enable checking of all the design specifications, ensuring 100% functional coverage. This paper deals with the design of Synchronous FIFO using Verilog. A FIFO (First-In-First-Out) is a memory queue, which controls the data flow between two modules. It has control logic embedded with it, which efficiently manages read and write operations. It has the capability to notify the concerned modules regarding its empty status and full status to help ensure no underflow or overflow of data. This FIFO design is classified as synchronous, as clocks control the read and write operations. Both read and write operations happen simultaneously using of Dual port RAM or an array of flip-flops in the design. After designing the Synchronous FIFO, its verification is carried out using the Universal Verification Methodology (UVM). A detailed discussion about the verification plan and test results is included

Verification of SD/MMC Controller IP Using UVM

Wide spread IP reuse in SoC Designs has enabled meteoric development of derivative designs. Several hardware block IPs are integrated together to reduce production costs, time-to-fab/timeto- market and achieve higher levels of productivity. These block IPs must be verified independently before shipping to ensure proper working and conformance to protocols that they are implementing. But, since the application of these IPs will vary from SoC to SoC, the verification environment must consider the important features and functions that are critical for that application. This may mean, revamping the entire testbench to verify the application critical features. Verification takes a major chunk of the total time of the manufacturing cycle. Thus, Verification IPs are created that can be re-used by making minor modifications to the existing test bench. In this project, an Open Cores IP – “SD/MMC Card Controller” (written in Verilog) is re-used by adding an interrupt line and card-detect feature and is verified using Universal Verification Methodology (UVM). The SD/MMC Card Controller has Wishbone as the Host Controller and SPI Master as the Core Controller. The test environment is layered and can be reused. This means, if this IP is re-designed to be controlled by another Host Controller (AXI for example), the verification environment can be re-used by inserting the BFM of that host controller. This paper discusses SD/MMC, Wishbone bus and SPI protocols, along with SD/MMC Controller and UVM based test-bench architecture

Design of an Efficient Design for Test (DFT) Architecture and it\u27s Verification Using Universal Verification Methodology

The complexity of the circuit design has been significantly increased from 1980’s till date, and until 80’s, due to less complexity and technology node being down to 180nm, the need for Design for Test (DFT) equipment was not as important. The few System on Chips (SoC) were tested using test patterns sent from the external test equipment. As the technology node shrunk further, the devices became faster and the complexity of S0C’s increased as the chip could accommodate more transistors. The SoC’s have become more vulnerable to physical defects. Quality factor became a major issue, which pushed the industry standard of the test coverage very high i.e. between 98% to 100%. To achieve such a high test coverage, testing the SoC’s by external test equipment demands high test time and test cost. Due to this reason, the DFT architectures within the chip have become popular demand in the industry. With the DFT architectures like Memory-Built In Self Test (MBIST) and Logic- Built In Self Test (LBIST), the memories and core logic embedded in the chip will undergo self test at the speed of functional clock and hence saving test time and test cost. Introducing DFT into the chip implies increase in area due to overhead and increase in power consumption due to additional pins. So, the DFT architectures need to be efficient. This project paper discusses about designing an efficient DFT architecture on SoC by integrating MBIST and LBIST with Joint Test Action Group-Test Access Port (JTAG-TAP) Controller and verifying using SysteVerilog (SV) and Universal Verification Methodologies (UVM) libraries. Detailed discussion of the design architecture and verification plan is included in the upcoming sections