The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud
getting more and more important

Vermaak, Hermanus Jacobus

University of Twente Research Information

English

A fast and low cost testing technique for core-based system-chips”,

A P1500 compliant BIST-based approach to embedded RAM Diagnosis”,

An Integrated System-on-Chip Test Framework”,

Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores,”

Critical Path Identification and Delay Tests of Dynamic Circuits”,

CTL—The Language for Describing Core-Based Test,” in

DEFUSE: A deterministic functional self-test methodology for processors”,

Delay Fault Testing for VLSI Circuits.”,

Delay-fault Testing of Embedded Cores using an Enhanced P1500 Compliant Wrapper”,

Delay-fault Testing of Embedded Cores”,

Design-for-Test for Digital IC,s and Embedded Core Systems”,

Digital Oscillation-Test Method for Delay and Stuck-at Fault Testing of Digital Circuits&quot;,

Effective and Efficient Test Architecture Design for SoCs ”,

Enhanced P1500 Compliant Wrapper suitable for Delay-fault Testing of Embedded Cores ”,

ETM10 Incorporates Hardware Segment of IEEE P1500”,

Instruction-level DFT for testing processor and IP cores in system-on-a-chip”,

Integrating BIST techniques for on-line SoC testing”,

Krstic et al,” Embedded Software-Based Self-Test for Programmable Core-Based Design”,

On variable-clock methods for path delay testing of sequential circuits,”

P1500-CTL: Towards a Standard Core Test Language”,

Test Requirements for Embedded Core-Based Systems and

Testing Embedded-Core Based System Chips”,

Testing for Delay Faults using a Variable Supply Voltage in Combination with the Oscillation Test Method ”,

Testing logic cores using a BIST P1500 compliant approach: a case of study,&quot;

Testing of core-based systems-on-a-chip”,

The Ability of Design-for-DelayTestability Structures to function in a environment with Process- and Application-Induced Variations”,

Towards a Standard for Embedded Core Test: An Example”,

Using a Pulsed Supply Voltage for Delay Faults Testing of Digital Circuits in a Digital Oscillation Environment”,

Using a Square Wave Supply Voltage to Detect Delay Faults in High Speed Digital circuits”,

Using the Oscillation Test Method to test for Delay Faults in Embedded Cores&quot;,

Design-for-delay-testability techniques for high-speed digital circuits