Optimal 2-D cell layout with integrated transistor folding

ABSTRACT Folding, a key requirement in high-performance cell layout, implies breaking a large transistor into smaller, equal-sized transistors (legs) that are connected in parallel and placed contiguously with diffusion sharing. We present a novel technique FCLIP that integrates folding into the generation of optimal layouts of CMOS cells in the twodimensional (2-D) style. FCLIP is based on integer linear programming (ILP) and precisely formulates cell width minimization as a 0-1 optimization problem. Folding is incorporated into the 0-1 ILP model by variables that represent the degrees of freedom that folding introduces into cell layout. FCLIP yields optimal results for three reasons: (1) it implicitly explores all possible transistor placements; (2) it considers all diffusion sharing possibilities among folded transistors; and (3) when paired P and N transistors have unequal numbers of legs, it considers all their relative positions. FCLIP is shown to be practical for relatively large circuits with up to 30 transistors. We then extend FCLIP to accommodate and-stack clustering, a requirement in most practical designs due to its benefits on circuit performance. This reduces run times dramatically, making FCLIP viable for much larger circuits. It also demonstrates the versatility of FCLIP's ILP-based approach in easily accommodating additional design constraints. INTRODUCTION Cell layout synthesis falls in the category of constrained optimization whose goal is to find a solution that optimizes some cost function under a set of constraints. The cost function can be the cell area, its delay, or a combination of these. The constraints include bounds on width or height, aspect ratio, number of diffusion rows, or the maximum size of transistors. Since cell layout optimization is NP-hard [3], any exact algorithm can, in the worst case, have an exponential run time. Therefore, most prior techniques for cell synthesis have avoided optimal algorithms in favor of faster, but less exact heuristic methods. Maziasz and Hayes FCLIP minimizes cell area in the following stages: First, transistors are folded based on user-specified limits on the maximum size of the P and N transistors. The input circuit is preprocessed to generate P/N pairs and identify and-stacks, that is, transistors that are connected in series. And-stack clustering is not only necessary in practical designs, but also reduces the complexity of the problem and, in turn, FCLIP's run times. Then an ILP model is formulated and solved to determine a 2-D layout of minimum width W min ; this model maximizes diffusion sharing among folded transistors and minimizes vertical inter-row connections. A second ILP model is then constructed to generate a layout that has width W min and minimum height, measured by the number of horizontal routing tracks. This paper only discusses 2-D cell width minimization with folding; however, FCLIP can be extended to minimize cell height also. FCLIP yields optimal results with folding for two reasons: (1) It implicitly explores all diffusion sharing possibilities among folded transistors; and (2) when paired P/N transistors have unequal numbers of legs, it considers all their relative positions. Not only does FCLIP support 2-D layout, it is superior to prior folding techniques proposed for 1-D layou