Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing

The development of computing systems based on the conventional von Neumann architecture has slowed down in the past decade as complementary metal-oxide-semiconductor (CMOS) technology scaling becomes more and more difficult. To satisfy the ever-increasing demands in computing power, neuromorphic computing has emerged as an attractive alternative. This dissertation focuses on developing learning algorithm, hardware architecture, circuit components, and design methodologies for low-power neuromorphic computing that can be employed in various energy-constrained applications. A top-down approach is adopted in this research. Starting from the algorithm-architecture co-design, a hardware-friendly learning algorithm is developed for spiking neural networks (SNNs). The possibility of estimating gradients from spike timings is explored. The learning algorithm is developed for the ease of hardware implementation, as well as the compatibility with many well-established learning techniques developed for classic artificial neural networks (ANNs). An SNN hardware equipped with the proposed on-chip learning algorithm is implemented in CMOS technology. In this design, two unique features of SNNs, the event-driven computation and the inferring with a progressive precision, are leveraged to reduce the energy consumption. In addition to low-power SNN hardware, accelerators for ANNs are also presented to accelerate the adaptive dynamic programing algorithm. An efficient and flexible single-instruction-multiple-data architecture is proposed to exploit the inherent data-level parallelism in the inference and learning of ANNs. In addition, the accelerator is augmented with a virtual update technique, which helps improve the throughput and energy efficiency remarkably. Lastly, two techniques in the architecture-circuit level are introduced to mitigate the degraded reliability of the memory system in a neuromorphic hardware owing to the aggressively-scaled supply voltage and integration density. The first method uses on-chip feedback to compensate for the process variation and the second technique improves the throughput and energy efficiency of a conventional error-correction method.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/144149/1/zhengn_1.pd

Monitor amb control strategies to reduce the impact of process variations in digital circuits

As CMOS technology scales down, Process, Voltage, Temperature and Ageing (PVTA) variations have an increasing impact on the performance and power consumption of electronic devices. These issues may hold back the continuous improvement of these devices in the near future. There are several ways to face the variability problem: to increase the operating margins of maximum clock frequency, the implementation of lithographic friendly layout styles, and the last one and the focus of this thesis, to adapt the circuit to its actual manufacturing and environment conditions by tuning some of the adjustable parameters once the circuit has been manufactured. The main challenge of this thesis is to develop a low-area variability compensation mechanism to automatically mitigate PVTA variations in run-time, i.e. while integrated circuit is running. This implies the development of a sensor to obtain the most accurate picture of variability, and the implementation of a control block to knob some of the electrical parameters of the circuit.A mesura que la tecnologia CMOS escala, les variacions de Procés, Voltatge, Temperatura i Envelliment (PVTA) tenen un impacte creixent en el rendiment i el consum de potència dels dispositius electrònics. Aquesta problemàtica podria arribar a frenar la millora contínua d'aquests dispositius en un futur proper. Hi ha diverses maneres d'afrontar el problema de la variabilitat: relaxar el marge de la freqüència màxima d'operació, implementar dissenys físics de xips més fàcils de litografiar, i per últim i com a tema principal d'aquesta tesi, adaptar el xip a les condicions de fabricació i d'entorn mitjançant la modificació d'algun dels seus paràmetres ajustables una vegada el circuit ja ha estat fabricat. El principal repte d'aquesta tesi és desenvolupar un mecanisme de compensació de variabilitat per tal de mitigar les variacions PVTA de manera automàtica en temps d'execució, és a dir, mentre el xip està funcionant. Això implica el desenvolupament d'un sensor capaç de mesurar la variabilitat de la manera més acurada possible, i la implementació d'un bloc de control que permeti l'ajust d'alguns dels paràmetres elèctrics dels circuits

Neuromorphic Engineering Editors' Pick 2021

This collection showcases well-received spontaneous articles from the past couple of years, which have been specially handpicked by our Chief Editors, Profs. André van Schaik and Bernabé Linares-Barranco. The work presented here highlights the broad diversity of research performed across the section and aims to put a spotlight on the main areas of interest. All research presented here displays strong advances in theory, experiment, and methodology with applications to compelling problems. This collection aims to further support Frontiers’ strong community by recognizing highly deserving authors

Energy Efficient Computing with Time-Based Digital Circuits

University of Minnesota Ph.D. dissertation. May 2019. Major: Electrical Engineering. Advisor: Chris Kim. 1 computer file (PDF); xv, 150 pages.Advancements in semiconductor technology have given the world economical, abundant, and reliable computing resources which have enabled countless breakthroughs in science, medicine, and agriculture which have improved the lives of many. Due to physics, the rate of these advancements is slowing, while the demand for the increasing computing horsepower ever grows. Novel computer architectures that leverage the foundation of conventional systems must become mainstream to continue providing the improved hardware required by engineers, scientists, and governments to innovate. This thesis provides a path forward by introducing multiple time-based computing architectures for a diverse range of applications. Simply put, time-based computing encodes the output of the computation in the time it takes to generate the result. Conventional systems encode this information in voltages across multiple signals; the performance of these systems is tightly coupled to improvements in semiconductor technology. Time-based computing elegantly uses the simplest of components from conventional systems to efficiently compute complex results. Two time-based neuromorphic computing platforms, based on a ring oscillator and a digital delay line, are described. An analog-to-digital converter is designed in the time domain using a beat frequency circuit which is used to record brain activity. A novel path planning architecture, with designs for 2D and 3D routes, is implemented in the time domain. Finally, a machine learning application using time domain inputs enables improved performance of heart rate prediction, biometric identification, and introduces a new method for using machine learning to predict temporal signal sequences. As these innovative architectures are presented, it will become clear the way forward will be increasingly enabled with time-based designs

Developing Organic Electrochemical Electronics from Fundamentals to Integrated Circuit Components

Heutzutage werden riesige Datenmengen zwischen Endgeräten und Cloud-Servern verschoben. Cloud-Computing war nach Bloomberg bereits für 1% des weltweiten Stromverbrauchs im Jahr 2021 verantwortlich. Darüber hinaus kann die monopolartige Speicherung personenbezogener Daten schwerwiegende Auswirkungen auf die Gesellschaften unserer Welt haben. Um persönlichen Datenschutz und einen nachhaltigen Energieverbrauch zu gewährleisten, bedarf es einer Datenverarbeitung direkt am Endgerät; bezeichnet als Edge Computing. In diesem Zuge wird die Nachfrage nach individuell gestalteten Edge-Geräten rapide ansteigen. Der neu entstehende Markt bietet der organischen elektrochemischen Elektronik eine große Chance, vor allem für bioelektronische Anwendungen; allerdings muss die Chipintegration verbessert werden. In dieser Arbeit habe ich elektrochemische organische Elektronik für die Integration in Computersysteme untersucht. Insbesondere habe ich einen festen, photostrukturierbaren Elektrolyten entwickelt, der die Integration von OECTs ohne Kreuzkommunikation zwischen Bauteilen ermöglicht. Die OECTs arbeiten bei Spannungen unter 1V und schalten mit einem großen An/Aus-Verhältnis von 5 Größenordnungen und einer Unterschwellenschwingung nahe des thermodynamischen Minimums von 60mV/Dekade. Darüber hinaus wurden bei der Untersuchung der Hysterese des Bauelements drei verschiedene Hystereseregime identifiziert. Anschließend untersuchte ich die Schaltdynamik des OECTs und demonstrierte ein Top-Gate-OECT mit einer maximalen Betriebsfrequenz von 1 kHz. Beim Versuch, die komplexe Wechselwirkung zwischen Ionen und Elektronen in integrierten OECTs zu verstehen, habe ich einen grundlegenden elektrochemischen Mechanismus identifiziert. Die Abhängigkeit dieses Mechanismus’ von der Gate-Größe und der Drain-Überlapplänge wurde aufgezeigt und dieses Wissen zur Optimierung elektrochemischer Inverter genutzt. Zur Darstellung von OECT-basierten Schaltungskomponenten habe ich verschiedene Halbleiter verwendet und entsprechende Inverter hergestellt. Schließlich wurde die Hysterese eines einzigen ambipolaren Inverters zur Demonstration eines dynamischen Klinkenschalters genutzt. Im Rahmen dieser Arbeit habe ich die OECT-Technologie von den Anfängen bis hin zu integrierten Schaltkreiskomponenten entwickelt. Ich glaube, dass diese Arbeit ein Startschuss für Wissenschaftler und Ingenieure sein wird, um die OECT-Technologie in der realen Welt des Edge Computing einzusetzen.Nowadays, vast amounts of data are shuttled between end-user devices and cloud servers. This cloud computing paradigm was, according to Bloomberg, already responsible for 1% of the world’s electricity usage in 2021. Moreover, the monopoly-like storage of personal data can have a severe impact on the world’s societies. To guarantee data privacy and sustainable energy consumption in future, data computation directly at the end-user site is mandatory. This computing paradigm is called edge computing. Owing to the vast amount of end-user-specific applications, the demand for individually designed edge devices will rapidly increase. In this newly approaching market, organic electrochemical electronics offer a great opportunity, especially for bioelectronic applications; however, the integration into low-power-consuming systems has to be improved. In this work, I investigated electrochemical organic electronics for their integration into computational systems. In particular, I developed a solid photopatternable electrolyte that allows integrating organic electrochemical transistors (OECTs) without cross-talk between adjacent devices. The OECTs operate at voltages below 1 V, and exhibit a large on/off ratio of 5 orders of magnitude and a subthreshold-swing close to the thermodynamic minimum of 60mV/dec. Moreover, investigating the device’s hysteresis, three distinct hysteresis regimes were identified; the RC-time-dominated regime I, the retention time governed regime II, and the time-independent stable regime III. I then examined the OECT’s switching dynamics and, subsequently, demonstrated a top-gate device with a maximum operating frequency of 1 kHz. Trying to understand the complex interaction between ions and electrons in integrated OECTs, I disclosed a fundamental electrochemical mechanism and named it the electrochemical electrode coupling (EEC). The EEC’s dependence on gate size and drain overlap length was rigorously shown, and this knowledge was used to optimize electrochemical inverters. Yet, to exemplify OECT-based circuit components, I employed various semiconductors and fabricated five inverters, each with its unique advantage. Finally, the ambipolar inverter’s hysteresis was used to demonstrate a single-device dynamic latch, a basic in-memory computational element. In this thesis, I developed the OECT technology from an infancy stage to integrated circuit components. I believe that this work will be a starting signal for scientists and engineers to bring the OECT technology into real-world edge computing

Multi-Scale Mathematical Modelling of Brain Networks in Alzheimer's Disease

Perturbations to brain network dynamics on a range of spatial and temporal scales are believed to underpin neurological disorders such as Alzheimer’s disease (AD). This thesis combines quantitative data analysis with tools such as dynamical systems and graph theory to understand how the network dynamics of the brain are altered in AD and experimental models of related pathologies. Firstly, we use a biophysical neuron model to elucidate ionic mechanisms underpinning alterations to the dynamics of principal neurons in the brain’s spatial navigation systems in an animal model of tauopathy. To uncover how synaptic deficits result in alterations to brain dynamics, we subsequently study an animal model featuring local and long-range synaptic degeneration. Synchronous activity (functional connectivity; FC) between neurons within a region of the cortex is analysed using two-photon calcium imaging data. Long-range FC between regions of the brain is analysed using EEG data. Furthermore, a computational model is used to study relationships between networks on these different spatial scales. The latter half of this thesis studies EEG to characterize alterations to macro-scale brain dynamics in clinical AD. Spectral and FC measures are correlated with cognitive test scores to study the hypothesis that impaired integration of the brain’s processing systems underpin cognitive impairment in AD. Whole brain computational modelling is used to gain insight into the role of spectral slowing on FC, and elucidate potential synaptic mechanisms of FC differences in AD. On a finer temporal scale, microstate analyses are used to identify changes to the rapid transitioning behaviour of the brain’s resting state in AD. Finally, the electrophysiological signatures of AD identified throughout the thesis are combined into a predictive model which can accurately separate people with AD and healthy controls based on their EEG, results which are validated on an independent patient cohort. Furthermore, we demonstrate in a small preliminary cohort that this model is a promising tool for predicting future conversion to AD in patients with mild cognitive impairment

Enabling high-performance, mixed-signal approximate computing

textFor decades, the semiconductor industry enjoyed exponential improvements in microprocessor power and performance with the device scaling of successive technology generations. Scaling limitations at sub-micron technologies, however, have ceased to provide these historical performance improvements within a limited power budget. While device scaling provides a larger number of transistors per chip, for the same chip area, a growing percentage of the chip will have to be powered off at any given time due to power constraints. As such, the architecture community has focused on energy-efficient designs and is looking to specialized hardware to provide gains in performance. A focus on energy efficiency, along with increasingly less reliable transistors due to device scaling, has led to research in the area of approximate computing, where accuracy is traded for energy efficiency when precise computation is not required. There is a growing body of approximation-tolerant applications that, for example, compute on noisy or incomplete data, such as real-world sensor inputs, or make approximations to decrease the computation load in the analysis of cumbersome data sets. These approximation-tolerant applications span application domains, such as machine learning, image processing, robotics, and financial analysis, among others. Since the advent of the modern processor, computing models have largely presumed the attribute of accuracy. A willingness to relax accuracy requirements, however, with goal of gaining energy efficiency, warrants the re-investigation of the potential of analog computing. Analog hardware offers the opportunity for fast and low-power computation; however, it presents challenges in the form of accuracy. Where analog compute blocks have been applied to solve fixed-function problems, general-purpose computing has relied on digital hardware implementations that provide generality and programmability. The work presented in this thesis aims to answer the following questions: Can analog circuits be successfully integrated into general-purpose computing to provide performance and energy savings? And, what is required to address the historical analog challenges of inaccuracy, programmability, and a lack of generality to enable such an approach? This thesis work investigates a neural approach as a means to address the historical analog challenges of inaccuracy, programmability, and generality and to enable the use of analog circuits in general-purpose, high-performance computing. The first piece of this thesis work investigates the use of analog circuits at the microarchitecture level in the form of an analog neural branch predictor. The task of branch prediction can tolerate imprecision, as roll-back mechanisms correct for branch mispredictions, and application-level accuracy remains unaffected. We show that analog circuits enable the implementation of a highly-accurate, neural-prediction algorithm that is infeasible to implement in the digital domain. The second piece of this thesis work presents a neural accelerator that targets approximation-tolerant code. Analog neural acceleration provides application speedup of 3.3x and energy savings of 12.1x with a quality loss less than 10% for all except one approximation-tolerant benchmark. These results show that, using a neural approach, analog circuits can be applied to provide performance and energy efficiency in high-performance, general-purpose computing.Computer Science

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

29th Annual Computational Neuroscience Meeting: CNS*2020

Meeting abstracts This publication was funded by OCNS. The Supplement Editors declare that they have no competing interests. Virtual | 18-22 July 202