Content Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing

As a promising alternative to the Von Neumann architecture, in-memory computing holds the promise of delivering high computing capacity while consuming low power. Content addressable memory (CAM) can implement pattern matching and distance measurement in memory with massive parallelism, making them highly desirable for data-intensive applications. In this paper, we propose and demonstrate a novel 1-transistor-per-bit CAM based on the ferroelectric reconfigurable transistor. By exploiting the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM can be realized in a single transistor. By eliminating the need for the complementary circuit, these non-volatile CAMs based on reconfigurable transistors can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multi-bit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and stored entries. Furthermore, utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real-time without changing the layout. These reconfigurable circuits will serve as important building blocks for high-density data-stream processors and reconfigurable Application-Specific Integrated Circuits (r-ASICs). The CAMs and transformable logic gates based on ferroelectric reconfigurable transistors will have broad applications in data-intensive applications from image processing to machine learning and artificial intelligence

Quantum computation over the butterfly network

In order to investigate distributed quantum computation under restricted network resources, we introduce a quantum computation task over the butterfly network where both quantum and classical communications are limited. We consider deterministically performing a two-qubit global unitary operation on two unknown inputs given at different nodes, with outputs at two distinct nodes. By using a particular resource setting introduced by M. Hayashi [Phys. Rev. A \textbf{76}, 040301(R) (2007)], which is capable of performing a swap operation by adding two maximally entangled qubits (ebits) between the two input nodes, we show that unitary operations can be performed without adding any entanglement resource, if and only if the unitary operations are locally unitary equivalent to controlled unitary operations. Our protocol is optimal in the sense that the unitary operations cannot be implemented if we relax the specifications of any of the channels. We also construct protocols for performing controlled traceless unitary operations with a 1-ebit resource and for performing global Clifford operations with a 2-ebit resource.Comment: 12 pages, 12 figures, the second version has been significantly expanded, and author ordering changed and the third version is a minor revision of the previous versio