3 research outputs found
HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis
Spin Transfer Torque Random Access Memory (STT-RAM) is an emerging
Non-Volatile Memory (NVM) technology that has garnered attention to overcome
the drawbacks of conventional CMOS-based technologies. However, such
technologies must be evaluated before deployment under real workloads and
architecture. But there is a lack of available open-source STT-RAM-based system
evaluation framework, which hampers research and experimentation and impacts
the adoption of STT- RAM in a system. This paper proposes a novel, extendable
STT-RAM memory controller design integrated inside the gem5 simulator. Our
framework enables understanding various aspects of STT-RAM, i.e., power, delay,
clock cycles, energy, and system throughput. We will open-source our HOPE
framework, which will fuel research and aid in accelerating the development of
future system architectures based on STT-RAM. It will also facilitate the user
for further tool enhancement