2 research outputs found
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking
Integrated circuits (ICs) are the foundation of all computing systems. They
comprise high-value hardware intellectual property (IP) that are at risk of
piracy, reverse-engineering, and modifications while making their way through
the geographically-distributed IC supply chain. On the frontier of hardware
security are various design-for-trust techniques that claim to protect designs
from untrusted entities across the design flow. Logic locking is one technique
that promises protection from the gamut of threats in IC manufacturing. In this
work, we perform a critical review of logic locking techniques in the
literature, and expose several shortcomings. Taking inspiration from other
cybersecurity competitions, we devise a community-led benchmarking exercise to
address the evaluation deficiencies. In reflecting on this process, we shed new
light on deficiencies in evaluation of logic locking and reveal important
future directions. The lessons learned can guide future endeavors in other
areas of hardware security
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix)
With recent advances in reverse engineering, attackers can reconstruct a
netlist to counterfeit chips by opening the die and scanning all layers of
authentic chips. This relatively easy counterfeiting is made possible by the
use of the standard simple clocking scheme, where all combinational blocks
function within one clock period, so that a netlist of combinational logic
gates and flip-flops is sufficient to duplicate a design. In this paper, we
propose to invalidate the assumption that a netlist completely represents the
function of a circuit with unconventional timing. With the introduced
wave-pipelining paths, attackers have to capture gate and interconnect delays
during reverse engineering, or to test a huge number of combinational paths to
identify the wave-pipelining paths. To hinder the test-based attack, we
construct false paths with wave-pipelining to increase the counterfeiting
challenge. Experimental results confirm that wave-pipelining true paths and
false paths can be constructed in benchmark circuits successfully with only a
negligible cost, thus thwarting the potential attack techniques