Design of a Neuromemristive Echo State Network Architecture

Echo state neural networks (ESNs) provide an efficient classification technique for spatiotemporal signals. The feedback connections in the ESN enable feature extraction in both spatial and temporal components in time series data. This property has been used in several application domains such as image and video analysis, anomaly detection, and speech recognition. The software implementations of the ESN demonstrated efficiency in processing such applications, and have low design cost and flexibility. However, hardware implementation is necessary for power constrained resources applications such as therapeutic and mobile devices. Moreover, software realization consumes an order or more power compared to the hardware realization. In this work, a hardware ESN architecture with neuromemristive system is proposed. A neuromemristive system is a brain inspired computing system that uses memristive devises for synaptic plasticity. The memristive devices in neuromemristive systems have several interesting properties such as small footprint, simple device structure, and most importantly zero static power dissipation. The proposed architecture is reconfigurable for different ESN topologies. 2-D mesh architecture and toroidal networks are exploited in the reservoir layer. The relation between performance of the proposed reservoir architecture and reservoir metrics are analyzed. The proposed architecture is tested on a suite of medical and human computer interaction applications. The benchmark suite includes epileptic seizure detection, speech emotion recognition, and electromyography (EMG) based finger motion recognition. The proposed ESN architecture demonstrated an accuracy of $90\%$, $96\%$, and $84\%$ for epileptic seizure detection, speech emotion recognition and EMG prosthetic fingers control respectively

Adaptive Integrated Circuit Design for Variation Resilience and Security

The past few decades witness the burgeoning development of integrated circuit in terms of process technology scaling. Along with the tremendous benefits coming from the scaling, challenges are also presented in various stages. During the design time, the complexity of developing a circuit with millions to billions of smaller size transistors is extended after the variations are taken into account. The difficulty of analyzing these nondeterministic properties makes the allocation scheme of redundant resource hardly work in a cost-efficient way. Besides fabrication variations, analog circuits are suffered from severe performance degradations owing to their physical attributes which are vulnerable to aging effects. As such, the post-silicon calibration approach gains increasing attentions to compensate the performance mismatch. For the user-end applications, additional system failures result from the pirated and counterfeited devices provided by the untrusted semiconductor supply chain. Again analog circuits show their weakness to this threat due to the shortage of piracy avoidance techniques. In this dissertation, we propose three adaptive integrated circuit designs to overcome these challenges respectively. The first one investigates the variability-aware gate implementation with the consideration of the overhead control of adaptivity assignment. This design improves the variation resilience typically for digital circuits while optimizing the power consumption and timing yield. The second design is implemented as a self-validation system for the calibration of diverse analog circuits. The system is completely integrated on chip to enhance the convenience without external assistance. In the last design, a classic analog component is further studied to establish the configurable locking mechanism for analog circuits. The use of Satisfiability Modulo Theories addresses the difficulty of searching the unique unlocking pattern of non-Boolean variables

A compact butterfly-style silicon photonic-electronic neural chip for hardware-efficient deep learning

The optical neural network (ONN) is a promising hardware platform for next-generation neurocomputing due to its high parallelism, low latency, and low energy consumption. Previous ONN architectures are mainly designed for general matrix multiplication (GEMM), leading to unnecessarily large area cost and high control complexity. Here, we move beyond classical GEMM-based ONNs and propose an optical subspace neural network (OSNN) architecture, which trades the universality of weight representation for lower optical component usage, area cost, and energy consumption. We devise a butterfly-style photonic-electronic neural chip to implement our OSNN with up to 7x fewer trainable optical components compared to GEMM-based ONNs. Additionally, a hardware-aware training framework is provided to minimize the required device programming precision, lessen the chip area, and boost the noise robustness. We experimentally demonstrate the utility of our neural chip in practical image recognition tasks, showing that a measured accuracy of 94.16% can be achieved in hand-written digit recognition tasks with 3-bit weight programming precision.Comment: 17 pages,5 figure