Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions

In the past decade, Convolutional Neural Networks (CNNs) have demonstrated state-of-the-art performance in various Artificial Intelligence tasks. To accelerate the experimentation and development of CNNs, several software frameworks have been released, primarily targeting power-hungry CPUs and GPUs. In this context, reconfigurable hardware in the form of FPGAs constitutes a potential alternative platform that can be integrated in the existing deep learning ecosystem to provide a tunable balance between performance, power consumption and programmability. In this paper, a survey of the existing CNN-to-FPGA toolflows is presented, comprising a comparative study of their key characteristics which include the supported applications, architectural choices, design space exploration methods and achieved performance. Moreover, major challenges and objectives introduced by the latest trends in CNN algorithmic research are identified and presented. Finally, a uniform evaluation methodology is proposed, aiming at the comprehensive, complete and in-depth evaluation of CNN-to-FPGA toolflows.Comment: Accepted for publication at the ACM Computing Surveys (CSUR) journal, 201

Efficient binary cutting packet classification

Packet classification is the process of distributing packets into ‘flows’ in an internet router. Router processes all packets which belong to predefined rule sets in similar manner& classify them to decide upon what all services packet should receive. It plays an important role in both edge and core routers to provideadvanced network service such as quality of service, firewalls and intrusion detection. These services require the ability to categorize & isolate packet traffic in different flows for proper processing. Packet classification remains a classical problem, even though lots of researcher working on the problem. Existing algorithms such asHyperCuts,boundary cutting and HiCuts have achieved an efficient performance by representing rules in geometrical method in a classifier and searching for a geometric subspace to which each inputpacket belongs. Some fixed interval-based cutting not relating to the actual space that eachrule covers is ineffective and results in a huge storage requirement. However, the memoryconsumption of these algorithms remains quite high when high throughput is required.Hence in this paper we are proposing a new efficient splitting criterion which is memory andtime efficient as compared to other mentioned techniques. Our proposed approach known as (ABC) Adaptive Binary Cuttingproducesa set of different-sized cuts at each decision step, with the goal to balance the distribution offilters and to reduce the filter duplication effect. The proposed algorithmuses stronger andmore straightforward criteria for decision treeconstruction. Experimental results will showthe effectiveness of proposed algorithm as compared to existing algorithm using differentparameters such as time & memory. In this paper, no symmetrical size cut at each decision node, with aim to make a distribution of filters balanced and also to reduce redundancy in filter

Automotive Ethernet Analyzer

Cílem této práce je navrhnout nástroj pro analýzu rozhraní 100Base-T1 (též známé jako Automotive Ethernet či BroadR-Reach). Práce je rozdělena do čtyř částí. V první části se seznámíme se standardem 100Base-T1 a čím se podobá a odlišuje od nejpoužívanějších standardů Ethernet. Následně na základě těchto znalostí navrhneme koncept jak pasivně monitorovat komunikaci na jednom síťovém segmentu tohoto rozhraní. Ve třetí části je popsána implementace potřebného hardware podle tohoto konceptu. Hardware je navržen tak, aby komunikoval s vývojovou sadou Terasic DE0-Nano-SoC. Poslední část popisuje návrh zdrojového kódu v jazyce VHDL, který dovoluje tomuto hardware fungovat a přeposílat zaznamenané pakety přes rozhraní Gigabit Ethernet, které je zabudované ve vývojové desce.The goal of this thesis is to design an analyzer tool for 100Base-T1 (also known as Automotive Ethernet or BroadR-Reach). It is split into four parts. In the first part, we acquaint ourselves with the 100Base-T1 standard and its intricacies, similarities and dissimilarities to most often used Ethernet standards. Next, based on this knowledge, we design a concept on how to passively monitor communication on a single network segment. In the third part the necessary hardware is implemented in accordance with said concept. The hardware interfaces to an FPGA development board Terasic DE0-Nano-SoC as per the assignment. The last part outlines the implementation of VHDL code that enables the hardware that was implemented to work and forward recorded packets over the development board's built-in Gigabit Ethernet interface