Towards a platform for FPGA implementation of the MLP based back propagation algorithm

This paper describes a new platform for FPGA implementation of the multilayer perceptron (MLP) back propagation algorithm (BP). The three implementation figures of the algorithm are considered. These are the off type implementation, the on chip global implementation and the dynamic reconfiguration of the ANN. To achieve our goal, a design for reuse strategy has been applied. To validate our approach, three case studies are considered using the Virtex-II and Virtex-4 FPGA devices. A comparative study is done and new conclusions are given