1 research outputs found
Mitigating Read-disturbance Errors in STT-RAM Caches by Using Data Compression
Due to its high density and close-to-SRAM read latency, spin transfer torque
RAM (STT-RAM) is considered one of the most-promising emerging memory
technologies for designing large last level caches (LLCs). However, in deep
sub-micron region, STT-RAM shows read-disturbance error (RDE) whereby a read
operation may modify the stored data value and this presents a severe threat to
performance and reliability of STT-RAM caches. In this paper, we present a
technique, named SHIELD, to mitigate RDE in STT-RAM LLCs. SHIELD uses data
compression to reduce number of read operations from STT-RAM blocks to avoid
RDE and also to reduce the number of bits written to cache during both write
and restore operations. Experimental results have shown that SHIELD provides
significant improvement in performance and energy efficiency. SHIELD consumes
smaller energy than two previous RDE-mitigation techniques, namely high-current
restore required read (HCRR, also called restore-after-read) and low-current
long latency read (LCLL) and even an ideal RDE-free STT-RAM cache.Comment: Book Chapte