DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

A case study for NoC based homogeneous MPSoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo

System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

An interprofessional nurse-led mental health promotion intervention for older home care clients with depressive symptoms.

BackgroundDepressive symptoms in older home care clients are common but poorly recognized and treated, resulting in adverse health outcomes, premature institutionalization, and costly use of health services. The objectives of this study were to examine the feasibility and acceptability of a new six-month interprofessional (IP) nurse-led mental health promotion intervention, and to explore its effects on reducing depressive symptoms in older home care clients (≥ 70 years) using personal support services.MethodsA prospective one-group pre-test/post-test study design was used. The intervention was a six-month evidence-based depression care management strategy led by a registered nurse that used an IP approach. Of 142 eligible consenting participants, 98 (69%) completed the six-month and 87 (61%) completed the one-year follow-up. Outcomes included depressive symptoms, anxiety, health-related quality of life (HRQoL), and the costs of use of all types of health services at baseline and six-month and one-year follow-up. An interpretive descriptive design was used to explore clients', nurses', and personal support workers' perceptions about the intervention's appropriateness, benefits, and barriers and facilitators to implementation.ResultsOf the 142 participants, 56% had clinically significant depressive symptoms, with 38% having moderate to severe symptoms. The intervention was feasible and acceptable to older home care clients with depressive symptoms. It was effective in reducing depressive symptoms and improving HRQoL at six-month follow-up, with small additional improvements six months after the intervention. The intervention also reduced anxiety at one year follow-up. Significant reductions were observed in the use of hospitalization, ambulance services, and emergency room visits over the study period.ConclusionsOur findings provide initial evidence for the feasibility, acceptability, and sustained effects of the nurse-led mental health promotion intervention in improving client outcomes, reducing use of expensive health services, and improving clinical practice behaviours of home care providers. Future research should evaluate its efficacy using a randomized clinical trial design, in different settings, with an adequate sample of older home care recipients with depressive symptoms.Trial registrationClinicaltrials.gov identifier: NCT01407926

Are IEEE 1500 compliant cores really compliant to the standard?

Functional verification of complex SoC designs is a challenging task, which fortunately is increasingly supported by automation. This article proposes a verification component for IEEE Std 1500, to be plugged into a commercial verification tool suit

A multiprocessor based packet-switch: performance analysis of the communication infrastructure

The intra-chip communication infrastructures are receiving always more attention since they are becoming a crucial part in the development of current SoCs. Due to the high availability of pre-characterized hard-IP, the complexity of the design is moving toward global interconnections which are introducing always more constraints at each technology node. Power consumption, timing closure, bandwidth requirements, time to market, are some of the factors that are leading to the proposal of new solutions for next generation multi-million SoCs. The need of high programmable systems and the high gate-count availability is moving always more attention on multiprocessors systems (MP-SoC) and so an adequate solution must be found for the communication infrastructure. One of the most promising technologies is the Network-On-Chip (NoC) architecture, which seems to better fit with the new demanding complexity of such systems. Before starting to develop new solutions, it is crucial to fully understand if and when current bus architectures introduce strong limitations in the development of high speed systems. This article describes a case study of a multiprocessor based ethernet packet-switch application with a shared-bus communication infrastructure. This system aims to depict all the bottlenecks which a shared-bus introduces under heavy load. What emerges from this analysis is that, as expected, a shared-bus is not scalable and it strongly limits whole system performances. These results strengthen the hypothesis that new communication architectures (like the NoC) must be found

The moderating effect of psychosocial factors in the relation between neighborhood walkability and children’s physical activity

BACKGROUND: The study aimed to investigate if psychosocial factors moderate the association between objective walkability and different domains of children's physical activity (PA). A second aim of the study was to investigate the direct associations between psychosocial factors and children's PA. Based on previous literature, it was hypothesized that walkability would be more strongly related to PA among children with negative psychosocial profiles. METHODS: Data were collected between December 2011 and May 2013 as part of the Belgian Environmental Physical Activity Study in children (BEPAS-child). In total, data from 494 children and one of their parents were included in the study. Children wore an accelerometer for 7 consecutive days and together with one of their parents, they completed the Flemish Physical Activity Questionnaire. Parents filled out a questionnaire concerning their child's psychosocial factors toward PA (i.e. parental attitude toward their child's PA, parental social norm toward their child's PA, parental support, friend support, children's self-efficacy, and perceived benefits and barriers toward sports and PA). Neighborhood walkability was calculated using geographical information systems (GIS). Multilevel cross-classified analyses were conducted. RESULTS: Of the 42 investigated interactions between neighborhood walkability and psychosocial factors in relation to PA among children, only 7 significant interactions were found of which 3 were only significant among children from low-income neighborhoods. Parental support and self-efficacy were positive correlates of children's PA in high- and low-income neighborhoods independent of the level of walkability, but effect sizes were small. CONCLUSIONS: The hypothesis that walkability would be more strongly related to PA among children with negative psychosocial profiles could not be confirmed and in general, psychosocial factors and objective walkability did not interact in relation to children's PA. Focusing on parental support and self-efficacy towards PA can possibly cause small effects on children's PA in both high- and low-walkable neighborhoods, as well as in high- and low-income neighborhoods