The ever increasing data rate of high speed I/Os has required higher test timing accuracy. In order to keep improving ATE’s edge placement accuracy, we have reviewed the traditional timing calibration methods in detail, and studied the timing error mechanism. Then we have developed a new calibration scheme to overcome the fundamental issues in some traditional calibration methods. Our main focus in this paper is on the following three areas: data dependent jitter (timing error), pin-to-pin skew and calibration at DUT