A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy

As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited channels. As a clock reconstructing module in a receiver, the recovered clock quality of Clock and Data Recovery is the main issue of the receiver performance. However, from unknown incoming jitter, it is difficult to optimize loop dynamics to minimize steady-state and dynamic jitter. In this thesis a 10 Gb/s adaptive loop bandwidth clock and data recovery circuit with on-chip loop filter is presented. The proposed system optimizes the loop bandwidth adaptively to minimize jitter so that it leads to an improved jitter tolerance performance. This architecture tunes the loop bandwidth by a factor of eight based on the phase information of incoming data. The resulting architecture performs as good as a maximum fixed loop bandwidth CDR while tracking high speed input jitter and as good as a minimum fixed bandwidth CDR while suppressing wide bandwidth steady-state jitter. By employing a mixed mode predictor, high updating rate loop bandwidth adaptation is achieved with low power consumption. Another relevant feature is that it integrates a typically large off-chip filter using a capacitance multiplication technique that employs dual charge pumps. The functionality of the proposed architecture has been verified through schematic and behavioral model simulations. In the simulation, the performance of jitter tolerance is confirmed that the proposed solution provides improved results and robustness to the variation of jitter profile. Its applicability to industrial standards is also verified by the jitter tolerance passing SONET OC-192 successfully

Analysis and Preliminary Design of an Advanced Technology Transport Flight Control System

The analysis and preliminary design of an advanced technology transport aircraft flight control system using avionics and flight control concepts appropriate to the 1980-1985 time period are discussed. Specifically, the techniques and requirements of the flight control system were established, a number of candidate configurations were defined, and an evaluation of these configurations was performed to establish a recommended approach. Candidate configurations based on redundant integration of various sensor types, computational methods, servo actuator arrangements and data-transfer techniques were defined to the functional module and piece-part level. Life-cycle costs, for the flight control configurations, as determined in an operational environment model for 200 aircraft over a 15-year service life, were the basis of the optimum configuration selection tradeoff. The recommended system concept is a quad digital computer configuration utilizing a small microprocessor for input/output control, a hexad skewed set of conventional sensors for body rate and body acceleration, and triple integrated actuators

Ultra-wideband Spread Spectrum Communications using Software Defined Radio and Surface Acoustic Wave Correlators

Ultra-wideband (UWB) communication technology offers inherent advantages such as the ability to coexist with previously allocated Federal Communications Commission (FCC) frequencies, simple transceiver architecture, and high performance in noisy environments. Spread spectrum techniques offer additional improvements beyond the conventional pulse-based UWB communications. This dissertation implements a multiple-access UWB communication system using a surface acoustic wave (SAW) correlator receiver with orthogonal frequency coding and software defined radio (SDR) base station transmitter. Orthogonal frequency coding (OFC) and pseudorandom noise (PN) coding provide a means for spreading of the UWB data. The use of orthogonal frequency coding (OFC) increases the correlator processing gain (PG) beyond that of code division multiple access (CDMA); providing added code diversity, improved pulse ambiguity, and superior performance in noisy environments. Use of SAW correlators reduces the complexity and power requirements of the receiver architecture by eliminating many of the components needed and reducing the signal processing and timing requirements necessary for digital matched filtering of the complex spreading signal. The OFC receiver correlator code sequence is hard-coded in the device due to the physical SAW implementation. The use of modern SDR forms a dynamic base station architecture which is able to programmatically generate a digitally modulated transmit signal. An embedded Xilinx Zynq ™ system on chip (SoC) technology was used to implement the SDR system; taking advantage of recent advances in digital-to-analog converter (DAC) sampling rates. SDR waveform samples are generated in baseband in-phase and quadrature (I & Q) pairs and upconverted to a 491.52 MHz operational frequency. The development of the OFC SAW correlator ultimately used in the receiver is presented along with a variety of advanced SAW correlator device embodiments. Each SAW correlator device was fabricated on lithium niobate (LiNbO3) with fractional bandwidths in excess of 20%. The SAW correlator device presented for use in system was implemented with a center frequency of 491.52 MHz; matching SDR transmit frequency. Parasitic electromagnetic feedthrough becomes problematic in the packaged SAW correlator after packaging and fixturing due to the wide bandwidths and high operational frequency. The techniques for reduction of parasitic feedthrough are discussed with before and after results showing approximately 10:1 improvement. Correlation and demodulation results are presented using the SAW correlator receiver under operation in an UWB communication system. Bipolar phase shift keying (BPSK) techniques demonstrate OFC modulation and demodulation for a test binary bit sequence. Matched OFC code reception is compared to a mismatched, or cross-correlated, sequence after correlation and demodulation. Finally, the signal-to-noise power ratio (SNR) performance results for the SAW correlator under corruption of a wideband noise source are presented

Severe storms observing satellite study

Payload distribution and the attitude control system for the multi-mission modular spacecraft/StormSat configuration are discussed. The design of the advanced atmospheric sounder and imaging radiometer (AASIR) gimbal drive and its servomechanism is described. Onboard data handling, data downlink communications, and ground data handling systems are developed. Additional topics covered include: magnetic unloading at synchronous altitude, north-south stationkeeping, and the feasibility and impact of flying the microwave atmospheric sounding radiometer (MASR) as an additional payload

Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System

With the number of transistors integrated into a single integrated circuit (IC) crossing the one-billion mark and complementary metal-oxide-semiconductor (CMOS) technology scaling pushing device dimensions ever-so-close to atomic scales, variability in transistor performance is becoming the dominant constraint in modern-day CMOS IC design. Developing novel approaches for device characterization, which allow a detailed study of electrical transistor characteristics across large statistical sample sets, is crucial for the proper identification, characterization, and modeling of different physical sources of device variability. On-chip characterization methodologies have the potential to address all of these issues by enabling the characterization of large statistical device sample sets, while also allowing for high measurement quality and throughput. In this work, a fully-integrated system for on-chip combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated test transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four-point Kelvin measurement technique with 12-bit sub-10 nA current measurement resolution, 10-bit sub-1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C-V characterization is performed using a novel leakage- and parasitics-insensitive charge-based capacitance measurement (CBCM) technique with atto-Farad resolution. The on-chip system is employed in developing a comprehensive CMOS transistor variability characterization methodology, studying both random and systematic sources of quasi-static device variability. For the first time, combined C-V/I-V characterization of circuit-representative devices is demonstrated and used to extract variations in the under- lying physical parameters of the device. Additionally, the fast current sampling capabilities of the system are used for the characterization of random telegraph noise (RTN) in small area devices. An automated methodology for the extraction of RTN parameters is developed, and the statistics of RTN are studied across device type, bias, and geometry

Miniature high dynamic range time-resolved CMOS SPAD image sensors

Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003, single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration quantum-level image sensors. Their unique feature of discerning single photon detections, their ability to retain temporal information on every collected photon and their amenability to high speed image sensor architectures makes them prime candidates for low light and time-resolved applications. From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge steps in detector and sensor architectures have been made to address the design challenges of pixel sensitivity and functionality trade-off, scalability and handling of large data rates. The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved applications with a small pixel pitch while maintaining both sensitivity and built -in functionality. Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing capability, smarter pixel designs with configurable functionality and novel system architectures that lift the processing burden off the pixel array and mediate data flow. Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS) achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection. Characterisation results of the detector and sensor performance are presented. Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal plane data processing and storage for high dynamic range as well as autonomous video rate operation. Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both architectures are discussed