3 research outputs found
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5 D, and 3D Processor-Memory Systems
Processing cores and the accompanying main memory working in tandem enable
the modern processors. Dissipating heat produced from computation, memory
access remains a significant problem for processors. Therefore, processor
thermal management continues to be an active research topic. Most thermal
management research takes place using simulations, given the challenges of
measuring temperature in real processors. Since core and memory are fabricated
on separate packages in most existing processors, with the memory having lower
power densities, thermal management research in processors has primarily
focused on the cores.
Memory bandwidth limitations associated with 2D processors lead to
high-density 2.5D and 3D packaging technology. 2.5D packaging places cores and
memory on the same package. 3D packaging technology takes it further by
stacking layers of memory on the top of cores themselves. Such packagings
significantly increase the power density, making processors prone to heating.
Therefore, mitigating thermal issues in high-density processors (packaged with
stacked memory) becomes an even more pressing problem. However, given the lack
of thermal modeling for memories in existing interval thermal simulation
toolchains, they are unsuitable for studying thermal management for
high-density processors.
To address this issue, we present CoMeT, the first integrated Core and Memory
interval Thermal simulation toolchain. CoMeT comprehensively supports thermal
simulation of high- and low-density processors corresponding to four different
core-memory configurations - off-chip DDR memory, off-chip 3D memory, 2.5D, and
3D. CoMeT supports several novel features that facilitate overlying system
research. Compared to an equivalent state-of-the-art core-only toolchain, CoMeT
adds only a ~5% simulation-time overhead. The source code of CoMeT has been
made open for public use under the MIT license.Comment: https://github.com/marg-tools/CoMe
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems
Processing cores and the accompanying main memory working in tandem enable modern processors. Dissipating heat produced from computation remains a significant problem for processors. Therefore, the thermal management of processors continues to be an active subject of research. Most thermal management research is performed using simulations, given the challenges in measuring temperatures in real processors. Fast yet accurate interval thermal simulation toolchains remain the research tool of choice to study thermal management in processors at the system level. However, the existing toolchains focus on the thermal management of cores in the processors, since they exhibit much higher power densities than memory.
The memory bandwidth limitations associated with 2D processors lead to high-density 2.5D and 3D packaging technology: 2.5D packaging technology places cores and memory on the same package; 3D packaging technology takes it further by stacking layers of memory on the top of cores themselves. These new packagings significantly increase the power density of the processors, making them prone to overheating. Therefore, mitigating thermal issues in high-density processors (packaged with stacked memory) becomes even more pressing. However, given the lack of thermal modeling for memories in existing interval thermal simulation toolchains, they are unsuitable for studying thermal management for high-density processors.
To address this issue, we present the first integrated Core and Memory interval Thermal (CoMeT) simulation toolchain. CoMeT comprehensively supports thermal simulation of high- and low-density processors corresponding to four different core-memory (integration) configurations-off-chip DDR memory, off-chip 3D memory, 2.5D, and 3D. CoMeT supports several novel features that facilitate overlying system research. CoMeT adds only an additional similar to 5% simulation-time overhead compared to an equivalent state-of-the-art core-only toolchain. The source code of CoMeT has been made open for public use under the MIT license
Thermal-Aware Design Techniques for Nanometer CMOS Circuits
Increase in chip power density results in higher operating temperatures, and thermal gradients (spatial and temporal) arise due to areas of the die with different power consumption. Thermal variations affect normal operation of nanoelectronic circuits in various dimensions, including reliability, leakage power and delay. And the picture will get more complicated (possibly worse) for CMOS devices with feature size below 45 nm. This paper provides an overview of some of the most recent design and synthesis techniques that will help in reducing the run-time temperature, as well as governing the effects of on-chip thermal gradients in the future generations of CMOS integrated circuit