Flexible and stretchable circuit technologies for space applications

Flexible and stretchable circuit technologies offer reduced volume and weight, increased electrical performance, larger design freedom and improved interconnect reliability. All of these advantages are appealing for space applications. In this paper, two example technologies, the ultra-thin chip package (UTCP) and stretchable moulded interconnect (SMI), are described. The UTCP technology results in a 60 µm thick chip package, including the embedding of a 20 µm thick chip, laser or protolithic via definition to the chip contacts and application of fan out metallization. Imec’s stretchable interconnect technology is inspired by conventional rigid and flexible printed circuit board (PCB) technology. Stretchable interconnects are realized by copper meanders supported by a flexible material e.g. polyimide. Elastic materials, predominantly silicone rubbers, are used to embed the conductors and the components, thus serving as circuit carrier. The possible advantages of these technologies with respect to space applications are discussed

Two- and Three-dimensional High Performance, Patterned Overlay Multi-chip Module Technology

A two- and three-dimensional multi-chip module technology was developed in response to the continuum in demand for increased performance in electronic systems, as well as the desire to reduce the size, weight, and power of space systems. Though developed to satisfy the needs of military programs, such as the Strategic Defense Initiative Organization, the technology, referred to as High Density Interconnect, can also be advantageously exploited for a wide variety of commercial applications, ranging from computer workstations to instrumentation and microwave telecommunications. The robustness of the technology, as well as its high performance, make this generality in application possible. More encouraging is the possibility of this technology for achieving low cost through high volume usage

Superconducting routing platform for large-scale integration of quantum technologies

To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspective in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies and low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented

Thermo-Mechanical Reliability and Electrical Performance of Indium Interconnects and Under Bump Metallization

This thesis presents reliability analysis of indium interconnects and Under Bump Metallization (UBM) in flip chip devices. Flip chip assemblies with the use of bump interconnections are frequently used, especially in high density, three-dimensional electronic devices. Currently there are many methods for interconnect bumping, all of which require UBM. The UBM is required for interconnection, diffusion resistance and quality electrical contact between substrate and device. Bonded silicon test vehicles were comprised of Indium bumps and three UBM compositions: Ti/Ni/Au (200\xc5/1000\xc5/500\xc5), Ti/Ni (200\xc5/1000\xc5), Ni (1000\xc5). UBM and indium were deposited by evaporation and exposed to unbiased accelerated temperature cycling(-55°C to 125°C, 15°C/min ramp rate). Finite Element Analysis (FEA) simulations were used to gain understanding of non-linear strain behavior of indium interconnects during temperature cycling. Experimental testing coupled with FEA simulations facilitated cycle-to-failure calculations. FEA results show plastic strain concentrations within indium bump below failure limits. It has been demonstrated that fabrication of Ti/Ni/Au, Ti/Ni, and Ni UBM stacks performed reliably within infant mortality failure region

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Integration of optical interconnections and optoelectronic components in flexible substrates

Licht als informatiedrager voor datacommunicatie kende een ongezien succes in de laatste decennia. Wegens de lage verliezen en hoge datasnelheden hebben ze voor het overbruggen van lange afstanden hun elektrische tegenhangers reeds geruime tijd verdrongen. Deze trend zet zich ook voort voor korte afstand communicatie op printplaten. Naast zijn functie als informatiedrager, wordt licht ook gebruikt om een waaier aan fysische grootheden te meten. Ook hier heeft licht enkele significante voordelen t.o.v elektrische informatiedragers, waardoor optische sensoren wijdverspreid zijn. Een tweede duidelijke trend binnen de elektronica is het gebruik van flexibele printkaarten. Deze zijn veel dunner, lichter en betrouwbaarder dan de klassieke harde printkaarten, waardoor ze uiterst geschikt zijn voor draagbare toepassingen waar compactheid en een laag gewicht hoge vereisten zijn. De flexibiliteit van de printplaten laat ook toe hen te gebruiken op onvlakke oppervlakken en op bewegende onderdelen. Het doel van het gepresenteerde doctoraatswerk is de ontwikkeling van een nieuw technologieplatform dat bovengenoemde trends combineert. Alle bouwblokken van optische communicatie, gaande van actieve opto-elektronische componenten, aanstuurelektronica, golfgeleiderbaantjes en galvanische verbindingen tot optische koppelstructuren tussen de verschillende bouwblokken, worden zodanig gerealiseerd dat elke component flexibel is en geïntegreerd wordt in een dunne folie met een dikte van slechts 150µm. Op die manier bekomen we een flexibele folie met alle passieve en actieve onderdelen voor optische communicatie geïntegreerd met enkel een elektrische interface naar de buitenwereld, wat de aanvaarding en toepassing van deze technologie in de huidige elektronica aanzienlijk kan versnellen. Binnen het doctoraatswerk werden alle voorgestelde technologieën en processen gerealiseerd en geoptimaliseerd. Bovendien werden de optische verliezen, warmteaspecten, hoogfrequent gedrag, mechanisch gedrag en betrouwbaarheid van de technologie gekarakteriseerd en vergeleken met de huidige state-of-the-art

Modeling, design, and characterization of through vias in silicon and glass interposers

Advancements in very large scale integration (VLSI) technology have led to unprecedented transistor and interconnect scaling. Further miniaturization by traditional IC scaling in future planar CMOS technology faces significant challenges. Stacking of ICs (3D IC) using three dimensional (3D) integration technology helps in significantly reducing wiring lengths, interconnect latency and power dissipation while reducing the size of the chip and enhancing performance. Interposer technology with ultra-fine pitch interconnections needs to be developed to support the huge I/O connection requirement for packaging 3D ICs. Through vias in stacked silicon ICs and interposers are the key components of a 3D system. The objective of this dissertation is to model through vias in 3D silicon and glass interposers and, to address power and high-speed signal integrity issues in 3D interposers considering silicon biasing effects. An equivalent circuit model of the through via in silicon interposer (Si TPV) has been proposed considering the bias voltage dependent Metal-Oxide-Semiconductor (MOS) capacitance effect. Important design guidelines and optimizations are proposed for Si TPVs used in the signal delivery network, power delivery network (PDN), and as variable capacitors. Through vias in glass interposers (Glass TPVs) are modeled, designed and simulated by using electromagnetic field solvers. Signal and power integrity analyses are performed for silicon and glass interposers. PDN design is proposed by utilizing the MOS capacitance of the Si TPVs for decoupling.PhDCommittee Chair: Tummala, Rao; Committee Co-Chair: Swaminathan, Madhavan; Committee Member: Lim, Sung Kyu; Committee Member: Mukhopadhyay, Saibal; Committee Member: Sitaraman, Suresh; Committee Member: Sundaram, Venk

Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.M.S.Committee Chair: Rao R. Tummala; Committee Member: C. P. Wong; Committee Member: P. M. Ra

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity