Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee re-liable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process varia-tion, some outlier chips are much slower than others and can-not be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the high-est supported (i.e., worst-case) DRAM temperature (85◦C). In this paper, we show that typical DRAM chips operating at typ-ical temperatures (e.g., 55◦C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case. Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve perfor-mance. Using an FPGA-based testing platform, we first char-acterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possi-ble to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8 % at 55◦C without sac-rificing correctness. Based on this characterization, we pro-pose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adaptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface. We evaluate AL-DRAM on a real system that allows us to re-configure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive work-loads by an average of 14 % without introducing any errors. We discuss and show why AL-DRAM does not compromise re-liability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance. 1