543 research outputs found
A system design approach toward integrated cryogenic quantum control systems
In this paper, we provide a system level perspective on the design of control
electronics for large scale quantum systems. Quantum computing systems with
high-fidelity control and readout, coherent coupling, calibrated gates, and
reconfigurable circuits with low error rates are expected to have superior
quantum volumes. Cryogenic CMOS plays a crucial role in the realization of
scalable quantum computers, by minimizing the feature size, lowering the cost,
power consumption, and implementing low latency error correction. Our approach
toward achieving scalable feed-back based control systems includes the design
of memory based arbitrary waveform generators (AWG's), wide band radio
frequency analog to digital converters, integrated amplifier chain, and state
discriminators that can be synchronized with gate sequences. Digitally assisted
designs, when implemented in an advanced CMOS node such as 7 nm can reap the
benefits of low power due to scaling. A qubit readout chain demands several
amplification stages before the digitizer. We propose the co-integration of our
in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required
gain at the digitizer input with minimal area. Our approach using high
impedance matching between the HEMT LNA and the cryogenic CMOS receiver can
relax the design constraints of an inverter-based CMOS LNA, paving the way
toward a fully integrated qubit readout chain. The qubit state discriminator
consists of a digital signal processor that computes the qubit state from the
digitizer output and a pre-determined threshold. The proposed system realizes
feedback-based optimal control for error mitigation and reduction of the
required data rate through the serial interface to room temperature
electronics
Real-Time Decoding for Fault-Tolerant Quantum Computing: Progress, Challenges and Outlook
Quantum computing is poised to solve practically useful problems which are
computationally intractable for classical supercomputers. However, the current
generation of quantum computers are limited by errors that may only partially
be mitigated by developing higher-quality qubits. Quantum error correction
(QEC) will thus be necessary to ensure fault tolerance. QEC protects the
logical information by cyclically measuring syndrome information about the
errors. An essential part of QEC is the decoder, which uses the syndrome to
compute the likely effect of the errors on the logical degrees of freedom and
provide a tentative correction. The decoder must be accurate, fast enough to
keep pace with the QEC cycle (e.g., on a microsecond timescale for
superconducting qubits) and with hard real-time system integration to support
logical operations. As such, real-time decoding is essential to realize
fault-tolerant quantum computing and to achieve quantum advantage. In this
work, we highlight some of the key challenges facing the implementation of
real-time decoders while providing a succinct summary of the progress to-date.
Furthermore, we lay out our perspective for the future development and provide
a possible roadmap for the field of real-time decoding in the next few years.
As the quantum hardware is anticipated to scale up, this perspective article
will provide a guidance for researchers, focusing on the most pressing issues
in real-time decoding and facilitating the development of solutions across
quantum and computer science
CMOS Quantum Computing: Toward A Quantum Computer System-on-Chip
Quantum computing is experiencing the transition from a scientific to an
engineering field with the promise to revolutionize an extensive range of
applications demanding high-performance computing. Many implementation
approaches have been pursued for quantum computing systems, where currently the
main streams can be identified based on superconducting, photonic, trapped-ion,
and semiconductor qubits. Semiconductor-based quantum computing, specifically
using CMOS technologies, is promising as it provides potential for the
integration of qubits with their control and readout circuits on a single chip.
This paves the way for the realization of a large-scale quantum computing
system for solving practical problems. In this paper, we present an overview
and future perspective of CMOS quantum computing, exploring developed
semiconductor qubit structures, quantum gates, as well as control and readout
circuits, with a focus on the promises and challenges of CMOS implementation
Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures
Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( ), referred to as “excess 1/f noise”, observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures
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