IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE The Performance and Experimental Results of a Multiple Bit Rate Symbol Timing Recovery Circuit for PSK Receivers

A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35pm Silicon Qn Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 3 10 pW. 1