An Improved LR-aided K-Best Algorithm for MIMO Detection

Recently, lattice reduction (LR) technique has caught great attention for multi-input multi-output (MIMO) receiver because of its low complexity and high performance. However, when the number of antennas is large, LR-aided linear detectors and successive interference cancellation (SIC) detectors still exhibit considerable performance gap to the optimal maximum likelihood detector (MLD). To enhance the performance of the LR-aided detectors, the LR-aided K-best algorithm was developed at the cost of the extra complexity on the order $\mathcal{O}(N_t^2 K + N_t K^2)$, where $N_t$ is the number of transmit antennas and $K$ is the number of candidates. In this paper, we develop an LR-aided K-best algorithm with lower complexity by exploiting a priority queue. With the aid of the priority queue, our analysis shows that the complexity of the LR-aided K-best algorithm can be further reduced to $\mathcal{O}(N_t^2 K + N_t K {\rm log}_2(K))$. The low complexity of the proposed LR-aided K-best algorithm allows us to perform the algorithm for large MIMO systems (e.g., 50x50 MIMO systems) with large candidate sizes. Simulations show that as the number of antennas increases, the error performance approaches that of AWGN channel.Comment: 5 pages, 4 figures, 1 table, conferenc

An Iterative Soft Decision Based LR-Aided MIMO Detector

The demand for wireless and high-rate communication system is increasing gradually and multiple-input-multiple-output (MIMO) is one of the feasible solutions to accommodate the growing demand for its spatial multiplexing and diversity gain. However, with high number of antennas, the computational and hardware complexity of MIMO increases exponentially. This accumulating complexity is a paramount problem in MIMO detection system directly leading to large power consumption. Hence, the major focus of this dissertation is algorithmic and hardware development of MIMO decoder with reduced complexity for both real and complex domain, which can be a beneficial solution with power efficiency and high throughput. Both hard and soft domain MIMO detectors are considered. The use of lattice reduction (LR) algorithm and on-demand-child-expansion for the reduction of noise propagation and node calculation respectively are the two of the key features of our developed architecture, presented in this literature. The real domain iterative soft MIMO decoding algorithm, simulated for 4 × 4 MIMO with different modulation scheme, achieves 1.1 to 2.7 dB improvement over Lease Sphere Decoder (LSD) and more than 8x reduction in list size, K as well as complexity of the detector. Next, the iterative real domain K-Best decoder is expanded to the complex domain with new detection scheme. It attains 6.9 to 8.0 dB improvement over real domain K-Best decoder and 1.4 to 2.5 dB better performance over conventional complex decoder for 8 × 8 MIMO with 64 QAM modulation scheme. Besides K, a new adjustable parameter, Rlimit has been introduced in order to append re-configurability trading-off between complexity and performance. After that, a novel low-power hardware architecture of complex decoder is developed for 8 × 8 MIMO and 64 QAM modulation scheme. The total word length of only 16 bits has been adopted limiting the bit error rate (BER) degradation to 0.3 dB with K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 580 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz. All of the proposed decoders mentioned above are bounded by the fixed K. Hence, an adaptive real domain K-Best decoder is further developed to achieve the similar performance with less K, thereby reducing the computational complexity of the decoder. It does not require accurate SNR measurement to perform the initial estimation of list size, K. Instead, the difference between the first two minimal distances is considered, which inherently eliminates complexity. In summary, a novel iterative K-Best detector for both real and complex domain with efficient VLSI design is proposed in this dissertation. The results from extensive simulation and VHDL with analysis using Synopsys tool are also presented for justification and validation of the proposed works

An Iterative Soft Decision Based LR-Aided MIMO Detector

The demand for wireless and high-rate communication system is increasing gradually and multiple-input-multiple-output (MIMO) is one of the feasible solutions to accommodate the growing demand for its spatial multiplexing and diversity gain. However, with high number of antennas, the computational and hardware complexity of MIMO increases exponentially. This accumulating complexity is a paramount problem in MIMO detection system directly leading to large power consumption. Hence, the major focus of this dissertation is algorithmic and hardware development of MIMO decoder with reduced complexity for both real and complex domain, which can be a beneficial solution with power efficiency and high throughput. Both hard and soft domain MIMO detectors are considered. The use of lattice reduction (LR) algorithm and on-demand-child-expansion for the reduction of noise propagation and node calculation respectively are the two of the key features of our developed architecture, presented in this literature. The real domain iterative soft MIMO decoding algorithm, simulated for 4 × 4 MIMO with different modulation scheme, achieves 1.1 to 2.7 dB improvement over Lease Sphere Decoder (LSD) and more than 8x reduction in list size, K as well as complexity of the detector. Next, the iterative real domain K-Best decoder is expanded to the complex domain with new detection scheme. It attains 6.9 to 8.0 dB improvement over real domain K-Best decoder and 1.4 to 2.5 dB better performance over conventional complex decoder for 8 × 8 MIMO with 64 QAM modulation scheme. Besides K, a new adjustable parameter, Rlimit has been introduced in order to append re-configurability trading-off between complexity and performance. After that, a novel low-power hardware architecture of complex decoder is developed for 8 × 8 MIMO and 64 QAM modulation scheme. The total word length of only 16 bits has been adopted limiting the bit error rate (BER) degradation to 0.3 dB with K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 580 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz. All of the proposed decoders mentioned above are bounded by the fixed K. Hence, an adaptive real domain K-Best decoder is further developed to achieve the similar performance with less K, thereby reducing the computational complexity of the decoder. It does not require accurate SNR measurement to perform the initial estimation of list size, K. Instead, the difference between the first two minimal distances is considered, which inherently eliminates complexity. In summary, a novel iterative K-Best detector for both real and complex domain with efficient VLSI design is proposed in this dissertation. The results from extensive simulation and VHDL with analysis using Synopsys tool are also presented for justification and validation of the proposed works

Design Exploration & Enhancements for Low Complexity Massive MIMO Detectors with High Modulation Order

Global energy consumed by communication and information technologies is expected to increase rapidly due to continuous usage of wireless standards and the expansion for their requirements [1]. In the next generation wireless communications, Multi Input and Multi Output (MIMO) systems are most promising technology to achieve high spectral efficiencies, while going past various challenges like resource and energy constraints [2]. There exists many detection algorithms like Maximum Likelihood (ML), Zero Forcing (ZF), Minimum Mean Square Error (MMSE) which have low silicon complexity but consume significant power for high-end MIMO systems, due to their high computational complexity. And then there are certain low power detection algorithms like real domain breadth first search K-best, with either conventional enumeration or Schnorr Euchner (SE) based enumeration. This improvement through either, comes with cost of comparatively high silicon complexity and sacrifices the performance in terms of detection bit error rate (BER). The complex domain equivalent may improve the BER performance but it’s dedicated algorithm ensures even higher silicon complexity. Several modifications have been performed on original complex domain K-best algorithm to decrease its high silicon complexity, retaining the better performance of the system. This work focuses on study and implementation of original real SE based K-best algorithm [3]. It also features my attempt to perform theoretical analysis of original complex domain detection algorithm, and to implement modified [4] and improved versions of complex domain to decrease its high silicon complexity, retaining BER performance. This work also focuses on exploration and implementation of past attempts on design modifications of complex domain algorithms and compare them across different attributes such as performance, computational and silicon complexity. Few system level and algorithmic level enhancements have been proposed and implemented for low complexity detectors explored. Dynamic fixed point iterative version of original real domain detector [3] has been studied and implemented, along with possible enhancements for complex domain detector. Pipelined hardware architecture of real domain SE based K-best detector [5] has also been studied as part of this work, with the intention of extending this to dynamic fixed point version and also complex domain detector