A self-routing non-buffering ATM switch.

by Timothy Kai-Cheung Chung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references.Chapter 1. --- INTRODUCTION --- p.1Chapter 2. --- ASYNCHRONOUS TRANSFER MODE SWITCHING --- p.4Chapter 2.1 --- Transfer Modes --- p.4Chapter 2.1.1 --- Circuit Switching --- p.4Chapter 2.1.2 --- ATM Switching --- p.6Chapter 2.1.3 --- Packet Switching --- p.8Chapter 2.2 --- Different Types of ATM Switching System --- p.8Chapter 2.2.1 --- Central Control Type --- p.9Chapter 2.2.2 --- Self-Routing Type --- p.9Chapter 2.3 --- Self-Routing Non-Buffering ATM Switching Node --- p.10Chapter 3. --- FUNCTIONAL DESCRIPTION OF MODULE ´بA´ة --- p.16Chapter 3.1 --- ATM Cell Format --- p.17Chapter 3.2 --- Concentrator --- p.17Chapter 3.3 --- Routing Cell --- p.19Chapter 4. --- PHYSICAL STRUCTURE OF MODULE ´بA´ة --- p.23Chapter 4.1 --- Clocking Scheme --- p.23Chapter 4.2 --- Concentrator --- p.25Chapter 4.2.1 --- 2-by-2 Sorter --- p.25Chapter 4.2.2 --- Input Framer --- p.30Chapter 4.2.3 --- Data Buffer --- p.38Chapter 4.3 --- Routing Cell --- p.38Chapter 4.3.1 --- Type I Router --- p.39Chapter 4.3.2 --- Type II Router --- p.42Chapter 4.4 --- Block By-Passed Function --- p.43Chapter 5. --- SIMULATION AND TEST --- p.48Chapter 5.1 --- Computer Simulation --- p.48Chapter 5.2 --- Actual Chip Testing --- p.53Chapter 5.3 --- Measurement Results --- p.55Chapter 5.3.1 --- Functionality --- p.55Chapter 5.3.2 --- Maximum Clock Frequency --- p.60Chapter 5.3.3 --- Power Dissipation --- p.61Chapter 6. --- CONCLUSION --- p.63Chapter A. --- BRIEF HISTORY OF ATM SWITCH ARCHITECTURE DEVELOPMENT --- p.65Chapter B. --- BIBLIOGRAPHY --- p.66Chapter C. --- A N-WELL CMOS PROCESS --- p.70Chapter D. --- CADENCE DESIGN FLOW --- p.73Chapter E. --- YERILOG SIMULATION PROGRAMS --- p.77Chapter F. --- SCHEMATIC DIAGRAMS --- p.10