The RDT network Router Chip

Design Outline The RDT network Router chip is a versatile router for the massively parallel computer prototype JUMP-1, which is currently under development by collaboration between 7 Japanese universities The major goal of this project is to establish techniques for building an ecient distributed shared memory on a massively parallel processor. For this purpose, the reduced hierarchical bit-map directory (RHBD) schemes In order to implement (RHBD) schemes eciently, we proposed a novel interconnection network RDT (Recursive Diagonal Torus) By using the 0.5BiCMOS SOG technology, it can transfer all packets synchronized with a unique CPU clock(60MHz). Long coaxial cables(4m at maximum) are directly driven with the ECL interface of this chip. Using the dual port RAM, packet buers allow to push and pull a it of the packet simultaneously. The mixed design approach with schematic and VHDL permits the development of the complicated chip with 90,522 gates in a year. 2 JUMP-1 and the RDT JUMP-1[1] consists of clusters connected with an interconnection network RDT 2.1 Interconnection network RD