Design of a large scale MIMD computer

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaves 43-44).by Eleni Kapogiannis.M.Eng

High Level Synthesis of Neural Network Chips

This thesis investigates the development of a silicon compiler dedicated to generate Application-Specific Neural Network Chips (ASNNCs) from a high level C-based behavioural specification language. The aim is to fully integrate the silicon compiler with the ESPRIT II Pygmalion neural programming environment. The integration of these two tools permits the translation of a neural network application specified in nC, the Pygmalion's C-based neural programming language, into either binary (for simulation) or silicon (for execution in hardware). Several applications benefit from this approach, in particular the ones that require real-time execution, for which a true neural computer is required. This research comprises two major parts: extension of the Pygmalion neural programming environment, to support automatic generation of neural network chips from the nC specification language; and implementation of the high level synthesis part of the neural silicon compiler. The extension of the neural programming environment has been developed to adapt the nC language to hardware constraints, and to provide the environment with a simulation tool to test in advance the performance of the neural chips. Firstly, new hardware-specific requisites have been incorporated to nC. However, special attention has been taken to avoid transforming nC into a hardware-oriented language, since the system assumes minimum (or even no) knowledge of VLSI design from the application developer. Secondly, a simulator for neural network hardware has been developed, which assesses how well the generated circuit will perform the neural computation. Lastly, a hardware library of neural network models associated with a target VLSI architecture has been built. The development of the neural silicon compiler focuses on the high level synthesis part of the process. The goal of the silicon compiler is to take nC as the input language and automatically translate it into one or more identical integrated circuits, which are specified in VHDL (the IEEE standard hardware description language) at the register transfer level. The development of the high level synthesis comprises four major parts: firstly, compilation and software-like optimisations of nC; secondly, transformation of the compiled code into a graph-based internal representation, which has been designed to be the basis for the hardware synthesis; thirdly, further transformations and hardware-like optimisations on the internal representation; and finally, creation of the neural chip's data path and control unit that implement the behaviour specified in nC. Special attention has been devoted to the creation of optimised hardware structures for the ASNNCs employing both phases of neural computing on-chip: recall and learning. This is achieved through the data path and control synthesis algorithms, which adopt a heuristic approach that targets the generated hardware structure of the neural chip in a specific VLSI architecture, namely the Generic Neuron. The viability, concerning the effective use of silicon area versus speed, has been evaluated through the automatic generation of a VHDL description for the neural chip employing the Back Propagation neural network model. This description is compared with the one created manually by a hardware designer

CIM: Revolution in Progress (Proceedings of the Final IIASA Conference on Computer Integrated Manufacturing: Technologies, Organizations and People in Transition)

The Final Conference of the IIASA Project on Computer Integrated Manufacturing was held at the headquarters of IIASA in Laxenburg, Austria, on July 1-4, 1990. The Conference itself was co-sponsored by the Ford and Alfred P. Sloan Foundations, though much of the earlier research work owes its existence to funding by the Finnish Sitra Organization and the American National Science Foundation. In addition to these primary funders, much of the work carried out by individual researchers was funded by their own governments, research institutes, etc., this included major inputs from Japan and Czechoslovakia. The aim of the research was to examine CIM from various perspectives including: technological characteristics, the diffusion process, managerial and organizational aspects, and the social and economic implications. The Conference was attended by 105 people from 22 countries, including representatives from the OECD, UNIDO, the ECE, and the ILO. Of these participants 28 came from Eastern Europe and the rest from Japan or Western countries. This Volume contains selected papers presented at the Conference, and transcripts of key parts of the policy discussion. The papers are organized in the following way: Part 1. Overviews; Part 2. Strategies and Models for CIM; Part 3. CIM Diffusion Studies; Part 4. CIM Technologies; Part 5. Organizational and Social Impacts; Part 6. Keynote Policy Panel Discussion; Part 7. CIM Implications for Industry and Government