On the Computational Complexity of MapReduce

In this paper we study MapReduce computations from a complexity-theoretic perspective. First, we formulate a uniform version of the MRC model of Karloff et al. (2010). We then show that the class of regular languages, and moreover all of sublogarithmic space, lies in constant round MRC. This result also applies to the MPC model of Andoni et al. (2014). In addition, we prove that, conditioned on a variant of the Exponential Time Hypothesis, there are strict hierarchies within MRC so that increasing the number of rounds or the amount of time per processor increases the power of MRC. To the best of our knowledge we are the first to approach the MapReduce model with complexity-theoretic techniques, and our work lays the foundation for further analysis relating MapReduce to established complexity classes

Lower Bounds for RAMs and Quantifier Elimination

We are considering RAMs $N_{n}$, with wordlength $n=2^{d}$, whose arithmetic instructions are the arithmetic operations multiplication and addition modulo $2^{n}$, the unary function $\min\lbrace 2^{x}, 2^{n}-1\rbrace$, the binary functions $\lfloor x/y\rfloor$ (with $\lfloor x/0 \rfloor =0$), $\max(x,y)$, $\min(x,y)$, and the boolean vector operations $\wedge,\vee,\neg$ defined on $0,1$ sequences of length $n$. It also has the other RAM instructions. The size of the memory is restricted only by the address space, that is, it is $2^{n}$ words. The RAMs has a finite instruction set, each instruction is encoded by a fixed natural number independently of $n$. Therefore a program $P$ can run on each machine $N_{n}$, if $n=2^{d}$ is sufficiently large. We show that there exists an $\epsilon>0$ and a program $P$, such that it satisfies the following two conditions. (i) For all sufficiently large $n=2^{d}$, if $P$ running on $N_{n}$ gets an input consisting of two words $a$ and $b$, then, in constant time, it gives a $0,1$ output $P_{n}(a,b)$. (ii) Suppose that $Q$ is a program such that for each sufficiently large $n=2^{d}$, if $Q$, running on $N_{n}$, gets a word $a$ of length $n$ as an input, then it decides whether there exists a word $b$ of length $n$ such that $P_{n}(a,b)=0$. Then, for infinitely many positive integers $d$, there exists a word $a$ of length $n=2^{d}$, such that the running time of $Q$ on $N_{n}$ at input $a$ is at least $\epsilon (\log d)^{\frac{1}{2}} (\log \log d)^{-1}$

Communication Complexity and Secure Function Evaluation

We suggest two new methodologies for the design of efficient secure protocols, that differ with respect to their underlying computational models. In one methodology we utilize the communication complexity tree (or branching for f and transform it into a secure protocol. In other words, "any function f that can be computed using communication complexity c can be can be computed securely using communication complexity that is polynomial in c and a security parameter". The second methodology uses the circuit computing f, enhanced with look-up tables as its underlying computational model. It is possible to simulate any RAM machine in this model with polylogarithmic blowup. Hence it is possible to start with a computation of f on a RAM machine and transform it into a secure protocol. We show many applications of these new methodologies resulting in protocols efficient either in communication or in computation. In particular, we exemplify a protocol for the "millionaires problem", where two participants want to compare their values but reveal no other information. Our protocol is more efficient than previously known ones in either communication or computation

Automata theoretic aspects of temporal behaviour and computability in logical neural networks

Imperial Users onl

Hierarchies and Space Measures for Pointer Machines

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryAir Force Institute of Technology, AFIT/CIR

Formal verification of a microcoded VIPER microprocessor using HOL

The Royal Signals and Radar Establishment (RSRE) and members of the Hardware Verification Group at Cambridge University conducted a joint effort to prove the correspondence between the electronic block model and the top level specification of Viper. Unfortunately, the proof became too complex and unmanageable within the given time and funding constraints, and is thus incomplete as of the date of this report. This report describes an independent attempt to use the HOL (Cambridge Higher Order Logic) mechanical verifier to verify Viper. Deriving from recent results in hardware verification research at UC Davis, the approach has been to redesign the electronic block model to make it microcoded and to structure the proof in a series of decreasingly abstract interpreter levels, the lowest being the electronic block level. The highest level is the RSRE Viper instruction set. Owing to the new approach and some results on the proof of generic interpreters as applied to simple microprocessors, this attempt required an effort approximately an order of magnitude less than the previous one

Mathematical Logic: Proof Theory, Constructive Mathematics

[no abstract available