The Impact of Deuterated CMOS processing on Gate Oxide Reliability

In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. In particular, the influence of deuterium incorporation on the bulk oxide quality is not clear. In this letter, deuterium or hydrogen is introduced during either the gate oxidation, postoxidation anneal, and/or the postmetal anneal (PMA). The oxide bulk degradation was evaluated using charge-to-breakdown and stress-induced leakage current; and the oxide interface degradation using hot-carrier degradation and low-frequency noise. The obtained results show that the oxide bulk does not benefit from the presence of deuterium, regardless of the stage of deuterium introduction, or the gate oxide thickness. The oxide interface is more stable only when deuterium is introduced in the PMA

Minority Carrier Tunneling and Stress-Induced Leakage Current for p+ gate MOS Capacitors with Poly-Si and PolySi0.7Ge0.3 Gate Material

In this paper the I-V conduction mechanism for gate injection (-V g), Stress-Induced Leakage Current (SILC) characteristics and time-to-breakdown (tbd) of PMOS capacitors with p+-poly-Si and poly-SiGe gate material on 5.6, 4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier Tunneling (MCT) from the gate is proposed for the I-V and SILC characteristics at -Vg of our devices. Time-to-breakdown data are presented and discusse

Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies

The historical evolution of hot carrier degradation mechanisms and their physical models are reviewed and an energy-driven hot carrier aging model is verified that can reproduce 62-nm-gate-long hot carrier degradation of transistors through consistent aging-parameter extractions for circuit simulation. A long-term hot carrier-resistant circuit design can be realized via optimal driver strength controls. The central role of the V GS ratio is emphasized during practical case studies on CMOS inverter chains and a dynamic random access memory (DRAM) word-line circuit. Negative bias temperature instability (NBTI) mechanisms are also reviewed and implemented in a hydrogen reaction-diffusion (R-D) framework. The R-D simulation reproduces time-dependent NBTI degradations interpreted into interface trap generation, Δ N it with a proper power-law dependency on time. The experimental evidence of pre-existing hydrogen-induced Si–H bond breakage is also proven by the quantifying R-D simulation. From this analysis, a low-pressure end-of-line (EOL) anneal can reduce the saturation level of NBTI degradation, which is believed to be caused by the outward diffusion of hydrogen from the gate regions and therefore prevents further breakage of Si–H bonds in the silicon-oxide interfaces

High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 ¿m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent ¿on¿/¿off¿ currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitutio

Deuterium in the gate dielectric of CMOS devices

Most of the electronic integrated circuits used today are Complementary MOS (CMOS) circuits, which consist mainly of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). In the last forty years there has been a tremendous reduction of the MOSFET dimensions.\ud This reduction will continue, enabling even faster and more complex integrated circuits. But, there are a number of hurdles on the road. One of these hurdles is the thickness reduction of an essential electrically isolating layer inside the MOSFET, the so-called gate dielectric. This gate dielectric is becoming so thin, it starts to leak electrical current under operating conditions. This increases the power consumption and can lead to a non-functional transistor. Reliability is also of concern, because the gate dielectric deteriorates under device operation, leading to even larger leakage currents.\u

Investigation of Thermal Stress Degradation in Indium-Gallium-Zinc-Oxide TFTs

The performance of IGZO TFTs has improved significantly in recent years, however device stability still remains a significant issue. Thermal stability of IGZO TFTs be- comes very crucial to ensure desired performance of end-product. Both bottom-gate (BG) and double-gate (DG) TFTs were observed to degrade with hotplate treatments under 200◦C. Such events are rarely reported in the literature, and thus became the primary focus of this work. The mechanism causing the instability is not completely understood, however experimental results indicate the instability occurs either di- rectly or indirectly due to the influence of H2O within the passivation oxide above the IGZO channel region. DG TFTs saw more pronounced degradation, which led to the hypothesis that there may be a reaction of the top gate metal with H2O molecules in the passivation oxide, liberating monatomic hydrogen. Both H2O and hydrogen behave as donor states in IGZO, thus rendering the channel more conduc- tive. The thermal stability also demonstrated a dependence on channel length, with shorter channel devices showing greater stability. This may be due to the metalized source/drain regions acting as effective getter to water during a 400◦C passivation anneal which is performed prior to top-gate metal deposition. This hypothesis led to an investigation on atomic layer deposition (ALD) of capping layers over the passiva- tion oxide of IGZO TFTs to act as an effective barrier to water/hydrogen migrating to the underlying IGZO channel

Interpretation and Physical Modeling of Electronic Transport and Defect States in IGZO Thin-Film Transistors

This work is a comprehensive study on the interpretation and modeling of electronic transport behavior and defect states in indium-gallium-zinc-oxide (IGZO) TFTs. Key studies have focused on advancing the state of IGZO TFTs by addressing several challenges in device stability, scaling, and device modeling. These studies have provided new insight on the associated mechanisms and have resulted in the realization of scaled thin-film transistors that exhibit excellent electrical performance and stability. This work has demonstrated the ability to scale the conventional inverted staggered IGZO TFT down to one micron channel length, with excellent on-state and off-state performance where the VT ≈1 V, µeff =12 cm2/Vs, Ileak ≤ 10-12 A/µm and SS ≈ 160 mV/dec. The working source/drain electrodes are direct metal contact regions to the IGZO, which requires several microns of gate overlap to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. New results utilizing ion implantation for self-aligned source/drain regions present a path towards submicron channel length. This strategy offers a reduction in channel length as well as parasitic capacitance, which translates to improvement in RC delay and associated voltage losses due to charge-sharing. The realization of self-aligned TFTs using boron ion implantation for selective activation was introduced in a first-time report of boron-doped IGZO. Cryogenic measurements made on long-channel devices has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. A completely new device model using Silvaco Atlas has been established which properly accounts for the role of donor-like oxygen vacancy defects, acceptor-like band-tail states, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The developed model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. A power-law fit for the µch = f(T) relationship, which resembles 〖μ ~ T〗^((+3)⁄2) behavior consistent with ionized defect scattering. The mobility model is expressly independent of carrier concentration, without dependence on the applied gate bias. The device model is consistent with a compact model developed for circuit simulation (SPICE) that has been recently refined to include on-state and off-state operation. While IGZO is the only AOS technology mature enough for commercialization, the effective electron channel mobility µeff ~ 10 cm2/Vs presents a performance limitation. Other candidate AOS materials which have higher reported channel mobility values have also been investigated; specifically, indium-tungsten-oxide (IWO) and indium-gallium-tin-oxide (ITGO). These investigations serve as preliminary studies; device characteristics support the claims of high channel mobility; however the influence of defect states clearly indicates the need for further process development. The advancements realized in IGZO TFTs in this work will serve as a foundation for these alternative AOS materials

A Study on Copper-Gate Integration with Titanium Interface Layers for IGZO TFTs

The continuous demand for ultra-high resolution and improved video performance on increasingly larger active-matrix displays has advanced the research field of thin film transistors (TFTs) materials, processes and devices. Performance improvements demonstrated by amorphous Indium-Gallium-Zinc-Oxide (IGZO) TSTs has enabled a commercialized backplane technology adopted for AM-OLED displays, providing advantage in device performance and uniformity at a much lower cost than Low Temperature Poly-crystalline Silicon (LTPS). However as the display size gets larger and the pixel density increases, charge transfer from the column driver to the pixel through the addressed row TFT within the required time interval becomes increasingly difficult. As the pixel size shrinks and the panel size grows, interconnects that must be scaled down in cross-section have to transport charge over longer distances.In addition, as the numbers of rows increase in a display, the time allowed for charge transfer decreases to maintain a high image refresh frequency. These challenges must be addressed by lower interconnect delay, thus the advantages in transitioning to Cu for long interconnect rows and columns. The gate electrodes are usually implemented as an appendage of the row interconnect, thus Cu-gate TFTS would avoid added process complexity while supporting high-speed interconnects and low production costs. The following work presents a study on Cu-gate integration and potential channel contamination on bottom-gate IGZO TSTs with a newly established baseline process. Cu was used in place to Mo as the gate electrode, with an underlying Ti layer to promote adhesion to the oxidized silicon substrate. The experimental design input factors included the option of a Ti capping layer on the Cu-gate, and the anneal conditions of the gate dielectric (PECVD SiO2) prior to IGZO sputtering. Distinct differences in physical and electrical responses over all treatment combinations were identified. Experimental results demonstrated that while the Ti capping layer promoted adhesion to the gate dielectric, it served as a source of contamination on pre-annealed treatments causing pronounced electrical characteristic shifting and dielectric failure. The anneal process was found to promote adhesion between the Cu-gate and the gate oxide without the use of Ti capping layer, as well as reduce oxide charge levels. Copper contamination did not appear to be an issue in treatment conditions at or below 400C, however pitting of the gate electrode occurred at anneal temperature above 400C, as well as electrical results that suggest evidence of Cu contamination. Visual observations and electrical characteristics are presented wit ha detailed discussion on comparisons between treatment combinations, with reference to the baseline IGZO devices