2,018 research outputs found
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
Neuromorphic computing systems comprise networks of neurons that use
asynchronous events for both computation and communication. This type of
representation offers several advantages in terms of bandwidth and power
consumption in neuromorphic electronic systems. However, managing the traffic
of asynchronous events in large scale systems is a daunting task, both in terms
of circuit complexity and memory requirements. Here we present a novel routing
methodology that employs both hierarchical and mesh routing strategies and
combines heterogeneous memory structures for minimizing both memory
requirements and latency, while maximizing programming flexibility to support a
wide range of event-based neural network architectures, through parameter
configuration. We validated the proposed scheme in a prototype multi-core
neuromorphic processor chip that employs hybrid analog/digital circuits for
emulating synapse and neuron dynamics together with asynchronous digital
circuits for managing the address-event traffic. We present a theoretical
analysis of the proposed connectivity scheme, describe the methods and circuits
used to implement such scheme, and characterize the prototype chip. Finally, we
demonstrate the use of the neuromorphic processor with a convolutional neural
network for the real-time classification of visual symbols being flashed to a
dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure
A Heterogeneous Parallel Non-von Neumann Architecture System for Accurate and Efficient Machine Learning Molecular Dynamics
This paper proposes a special-purpose system to achieve high-accuracy and
high-efficiency machine learning (ML) molecular dynamics (MD) calculations. The
system consists of field programmable gate array (FPGA) and application
specific integrated circuit (ASIC) working in heterogeneous parallelization. To
be specific, a multiplication-less neural network (NN) is deployed on the
non-von Neumann (NvN)-based ASIC (SilTerra 180 nm process) to evaluate atomic
forces, which is the most computationally expensive part of MD. All other
calculations of MD are done using FPGA (Xilinx XC7Z100). It is shown that, to
achieve similar-level accuracy, the proposed NvN-based system based on low-end
fabrication technologies (180 nm) is 1.6x faster and 10^2-10^3x more energy
efficiency than state-of-the-art vN based MLMD using graphics processing units
(GPUs) based on much more advanced technologies (12 nm), indicating superiority
of the proposed NvN-based heterogeneous parallel architecture
New Logic-In-Memory Paradigms: An Architectural and Technological Perspective
Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal-oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm
The Landscape of Compute-near-memory and Compute-in-memory: A Research and Commercial Overview
In today's data-centric world, where data fuels numerous application domains,
with machine learning at the forefront, handling the enormous volume of data
efficiently in terms of time and energy presents a formidable challenge.
Conventional computing systems and accelerators are continually being pushed to
their limits to stay competitive. In this context, computing near-memory (CNM)
and computing-in-memory (CIM) have emerged as potentially game-changing
paradigms. This survey introduces the basics of CNM and CIM architectures,
including their underlying technologies and working principles. We focus
particularly on CIM and CNM architectures that have either been prototyped or
commercialized. While surveying the evolving CIM and CNM landscape in academia
and industry, we discuss the potential benefits in terms of performance,
energy, and cost, along with the challenges associated with these cutting-edge
computing paradigms
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